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289e922582
Older versions of GCC really want to know the full definition
of the type involved in rcu_assign_pointer().
struct dpll_pin is defined in a local header, net/core can't
reach it. Move all the netdev <> dpll code into dpll, where
the type is known. Otherwise we'd need multiple function calls
to jump between the compilation units.
This is the same problem the commit under fixes was trying to address,
but with rcu_assign_pointer() not rcu_dereference().
Some of the exports are not needed, networking core can't
be a module, we only need exports for the helpers used by
drivers.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Link: https://lore.kernel.org/all/35a869c8-52e8-177-1d4d-e57578b99b6@linux-m68k.org/
Fixes: 640f41ed33 ("dpll: fix build failure due to rcu_dereference_check() on unknown type")
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://lore.kernel.org/r/20240305013532.694866-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
552 lines
25 KiB
ReStructuredText
552 lines
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ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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===============================
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The Linux kernel dpll subsystem
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===============================
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DPLL
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====
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PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
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signal of a device with an external clock signal. Effectively enabling
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device to run on the same clock signal beat as provided on a PLL input.
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DPLL - Digital Phase Locked Loop is an integrated circuit which in
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addition to plain PLL behavior incorporates a digital phase detector
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and may have digital divider in the loop. As a result, the frequency on
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DPLL's input and output may be configurable.
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Subsystem
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=========
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The main purpose of dpll subsystem is to provide general interface
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to configure devices that use any kind of Digital PLL and could use
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different sources of input signal to synchronize to, as well as
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different types of outputs.
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The main interface is NETLINK_GENERIC based protocol with an event
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monitoring multicast group defined.
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Device object
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=============
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Single dpll device object means single Digital PLL circuit and bunch of
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connected pins.
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It reports the supported modes of operation and current status to the
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user in response to the `do` request of netlink command
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``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem
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with `dump` netlink request of the same command.
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Changing the configuration of dpll device is done with `do` request of
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netlink ``DPLL_CMD_DEVICE_SET`` command.
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A device handle is ``DPLL_A_ID``, it shall be provided to get or set
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configuration of particular device in the system. It can be obtained
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with a ``DPLL_CMD_DEVICE_GET`` `dump` request or
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a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide
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attributes that result in single device match.
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Pin object
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==========
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A pin is amorphic object which represents either input or output, it
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could be internal component of the device, as well as externally
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connected.
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The number of pins per dpll vary, but usually multiple pins shall be
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provided for a single dpll device.
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Pin's properties, capabilities and status is provided to the user in
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response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command.
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It is also possible to list all the pins that were registered in the
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system with `dump` request of ``DPLL_CMD_PIN_GET`` command.
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Configuration of a pin can be changed by `do` request of netlink
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``DPLL_CMD_PIN_SET`` command.
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Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set
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configuration of particular pin in the system. It can be obtained with
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``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do`
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request, where user provides attributes that result in single pin match.
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Pin selection
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=============
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In general, selected pin (the one which signal is driving the dpll
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device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only
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one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll
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device.
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Pin selection can be done either manually or automatically, depending
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on hardware capabilities and active dpll device work mode
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(``DPLL_A_MODE`` attribute). The consequence is that there are
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differences for each mode in terms of available pin states, as well as
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for the states the user can request for a dpll device.
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In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive
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one of following pin states:
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- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
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- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
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device
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In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or
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receive one of following pin states:
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- ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
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input for automatic selection algorithm
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- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
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a valid input for automatic selection algorithm
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In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive
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pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection
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algorithm locks a dpll device with one of the inputs.
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Shared pins
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===========
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A single pin object can be attached to multiple dpll devices.
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Then there are two groups of configuration knobs:
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1) Set on a pin - the configuration affects all dpll devices pin is
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registered to (i.e., ``DPLL_A_PIN_FREQUENCY``),
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2) Set on a pin-dpll tuple - the configuration affects only selected
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dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``,
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``DPLL_A_PIN_DIRECTION``).
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MUX-type pins
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=============
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A pin can be MUX-type, it aggregates child pins and serves as a pin
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multiplexer. One or more pins are registered with MUX-type instead of
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being directly registered to a dpll device.
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Pins registered with a MUX-type pin provide user with additional nested
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attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered
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with.
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If a pin was registered with multiple parent pins, they behave like a
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multiple output multiplexer. In this case output of a
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``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested
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attributes with current state related to each parent, like::
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'pin': [{{
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'clock-id': 282574471561216,
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'module-name': 'ice',
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'capabilities': 4,
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'id': 13,
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'parent-pin': [
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{'parent-id': 2, 'state': 'connected'},
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{'parent-id': 3, 'state': 'disconnected'}
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],
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'type': 'synce-eth-port'
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}}]
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Only one child pin can provide its signal to the parent MUX-type pin at
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a time, the selection is done by requesting change of a child pin state
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on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested
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attribute. Example of netlink `set state on parent pin` message format:
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========================== =============================================
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``DPLL_A_PIN_ID`` child pin id
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``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration
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related to parent pin
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``DPLL_A_PIN_PARENT_ID`` parent pin id
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``DPLL_A_PIN_STATE`` requested pin state on parent
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========================== =============================================
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Pin priority
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============
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Some devices might offer a capability of automatic pin selection mode
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(enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute).
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Usually, automatic selection is performed on the hardware level, which
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means only pins directly connected to the dpll can be used for automatic
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input pin selection.
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In automatic selection mode, the user cannot manually select a input
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pin for the device, instead the user shall provide all directly
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connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would
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pick a highest priority valid signal and use it to control the DPLL
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device. Example of netlink `set priority on parent pin` message format:
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============================ =============================================
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``DPLL_A_PIN_ID`` configured pin id
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``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration
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related to parent dpll device
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``DPLL_A_PIN_PARENT_ID`` parent dpll device id
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``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll
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============================ =============================================
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Child pin of MUX-type pin is not capable of automatic input pin selection,
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in order to configure active input of a MUX-type pin, the user needs to
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request desired pin state of the child pin on the parent pin,
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as described in the ``MUX-type pins`` chapter.
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Phase offset measurement and adjustment
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========================================
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Device may provide ability to measure a phase difference between signals
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on a pin and its parent dpll device. If pin-dpll phase offset measurement
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is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
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attribute for each parent dpll device.
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Device may also provide ability to adjust a signal phase on a pin.
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If pin phase adjustment is supported, minimal and maximal values that pin
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handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
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with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
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attributes. Configured phase adjust value is provided with
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``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
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requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
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=============================== ======================================
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``DPLL_A_PIN_ID`` configured pin id
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent dpll device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
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configuration on given parent dpll
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device
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``DPLL_A_PIN_PARENT_ID`` parent dpll device id
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``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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between a pin and parent dpll device
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=============================== ======================================
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All phase related values are provided in pico seconds, which represents
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time difference between signals phase. The negative value means that
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phase of signal on pin is earlier in time than dpll's signal. Positive
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value means that phase of signal on pin is later in time than signal of
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a dpll.
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Phase adjust (also min and max) values are integers, but measured phase
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offset values are fractional with 3-digit decimal places and shell be
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divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
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modulo divided to get fractional part.
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Configuration commands group
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============================
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Configuration commands are used to get information about registered
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dpll devices (and pins), as well as set configuration of device or pins.
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As dpll devices must be abstracted and reflect real hardware,
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there is no way to add new dpll device via netlink from user space and
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each device should be registered by its driver.
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All netlink commands require ``GENL_ADMIN_PERM``. This is to prevent
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any spamming/DoS from unauthorized userspace applications.
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List of netlink commands with possible attributes
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=================================================
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Constants identifying command types for dpll device uses a
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``DPLL_CMD_`` prefix and suffix according to command purpose.
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The dpll device related attributes use a ``DPLL_A_`` prefix and
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suffix according to attribute purpose.
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==================================== =================================
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``DPLL_CMD_DEVICE_ID_GET`` command to get device ID
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``DPLL_A_MODULE_NAME`` attr module name of registerer
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``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier
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(EUI-64), as defined by the
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IEEE 1588 standard
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``DPLL_A_TYPE`` attr type of dpll device
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==================================== =================================
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==================================== =================================
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``DPLL_CMD_DEVICE_GET`` command to get device info or
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dump list of available devices
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``DPLL_A_ID`` attr unique dpll device ID
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``DPLL_A_MODULE_NAME`` attr module name of registerer
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``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier
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(EUI-64), as defined by the
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IEEE 1588 standard
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``DPLL_A_MODE`` attr selection mode
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``DPLL_A_MODE_SUPPORTED`` attr available selection modes
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``DPLL_A_LOCK_STATUS`` attr dpll device lock status
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``DPLL_A_TEMP`` attr device temperature info
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``DPLL_A_TYPE`` attr type of dpll device
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==================================== =================================
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==================================== =================================
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``DPLL_CMD_DEVICE_SET`` command to set dpll device config
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``DPLL_A_ID`` attr internal dpll device index
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``DPLL_A_MODE`` attr selection mode to configure
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==================================== =================================
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Constants identifying command types for pins uses a
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``DPLL_CMD_PIN_`` prefix and suffix according to command purpose.
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The pin related attributes use a ``DPLL_A_PIN_`` prefix and suffix
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according to attribute purpose.
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==================================== =================================
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``DPLL_CMD_PIN_ID_GET`` command to get pin ID
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``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer
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``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier
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(EUI-64), as defined by the
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IEEE 1588 standard
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``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided
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by registerer
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``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided
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by registerer
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``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided
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by registerer
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``DPLL_A_PIN_TYPE`` attr type of a pin
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==================================== =================================
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==================================== ==================================
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``DPLL_CMD_PIN_GET`` command to get pin info or dump
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list of available pins
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``DPLL_A_PIN_ID`` attr unique a pin ID
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``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer
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``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier
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(EUI-64), as defined by the
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IEEE 1588 standard
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``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided
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by registerer
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``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided
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by registerer
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``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided
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by registerer
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``DPLL_A_PIN_TYPE`` attr type of a pin
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``DPLL_A_PIN_FREQUENCY`` attr current frequency of a pin
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``DPLL_A_PIN_FREQUENCY_SUPPORTED`` nested attr provides supported
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frequencies
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``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
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``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
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adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase
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adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device
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the pin is connected with
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``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
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``DPLL_A_PIN_PRIO`` attr priority of pin on the
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dpll device
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``DPLL_A_PIN_STATE`` attr state of pin on the parent
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dpll device
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``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
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parent dpll device
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``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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between a pin and parent dpll
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``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
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the pin is connected with
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``DPLL_A_PIN_PARENT_ID`` attr parent pin id
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``DPLL_A_PIN_STATE`` attr state of pin on the parent
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pin
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``DPLL_A_PIN_CAPABILITIES`` attr bitmask of pin capabilities
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==================================== ==================================
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==================================== =================================
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``DPLL_CMD_PIN_SET`` command to set pins configuration
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``DPLL_A_PIN_ID`` attr unique a pin ID
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``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin
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``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase
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adjustment on parent device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll
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device configuration request
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``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
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``DPLL_A_PIN_DIRECTION`` attr requested direction of a pin
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``DPLL_A_PIN_PRIO`` attr requested priority of pin on
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the dpll device
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``DPLL_A_PIN_STATE`` attr requested state of pin on
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the dpll device
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``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
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configuration request
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``DPLL_A_PIN_PARENT_ID`` attr parent pin id
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``DPLL_A_PIN_STATE`` attr requested state of pin on
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parent pin
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==================================== =================================
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Netlink dump requests
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=====================
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The ``DPLL_CMD_DEVICE_GET`` and ``DPLL_CMD_PIN_GET`` commands are
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capable of dump type netlink requests, in which case the response is in
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the same format as for their ``do`` request, but every device or pin
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registered in the system is returned.
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SET commands format
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===================
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``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides
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``DPLL_A_ID``, which is unique identifier of dpll device in the system,
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as well as parameter being configured (``DPLL_A_MODE``).
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``DPLL_CMD_PIN_SET`` - to target a pin user must provide a
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``DPLL_A_PIN_ID``, which is unique identifier of a pin in the system.
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Also configured pin parameters must be added.
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If ``DPLL_A_PIN_FREQUENCY`` is configured, this affects all the dpll
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devices that are connected with the pin, that is why frequency attribute
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shall not be enclosed in ``DPLL_A_PIN_PARENT_DEVICE``.
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Other attributes: ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE`` or
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``DPLL_A_PIN_DIRECTION`` must be enclosed in
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``DPLL_A_PIN_PARENT_DEVICE`` as their configuration relates to only one
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of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is
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also required inside that nest.
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For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in
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similar way, by enclosing required state in ``DPLL_A_PIN_PARENT_PIN``
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nested attribute and targeted parent pin id in ``DPLL_A_PIN_PARENT_ID``.
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In general, it is possible to configure multiple parameters at once, but
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internally each parameter change will be invoked separately, where order
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of configuration is not guaranteed by any means.
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Configuration pre-defined enums
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===============================
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.. kernel-doc:: include/uapi/linux/dpll.h
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Notifications
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=============
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dpll device can provide notifications regarding status changes of the
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device, i.e. lock status changes, input/output changes or other alarms.
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There is one multicast group that is used to notify user-space apps via
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netlink socket: ``DPLL_MCGRP_MONITOR``
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Notifications messages:
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============================== =====================================
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``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created
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``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted
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``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed
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``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created
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``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted
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``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed
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============================== =====================================
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Events format is the same as for the corresponding get command.
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Format of ``DPLL_CMD_DEVICE_`` events is the same as response of
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``DPLL_CMD_DEVICE_GET``.
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Format of ``DPLL_CMD_PIN_`` events is same as response of
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``DPLL_CMD_PIN_GET``.
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Device driver implementation
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============================
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Device is allocated by dpll_device_get() call. Second call with the
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same arguments will not create new object but provides pointer to
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previously created device for given arguments, it also increases
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refcount of that object.
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Device is deallocated by dpll_device_put() call, which first
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decreases the refcount, once refcount is cleared the object is
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destroyed.
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Device should implement set of operations and register device via
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dpll_device_register() at which point it becomes available to the
|
|
users. Multiple driver instances can obtain reference to it with
|
|
dpll_device_get(), as well as register dpll device with their own
|
|
ops and priv.
|
|
|
|
The pins are allocated separately with dpll_pin_get(), it works
|
|
similarly to dpll_device_get(). Function first creates object and then
|
|
for each call with the same arguments only the object refcount
|
|
increases. Also dpll_pin_put() works similarly to dpll_device_put().
|
|
|
|
A pin can be registered with parent dpll device or parent pin, depending
|
|
on hardware needs. Each registration requires registerer to provide set
|
|
of pin callbacks, and private data pointer for calling them:
|
|
|
|
- dpll_pin_register() - register pin with a dpll device,
|
|
- dpll_pin_on_pin_register() - register pin with another MUX type pin.
|
|
|
|
Notifications of adding or removing dpll devices are created within
|
|
subsystem itself.
|
|
Notifications about registering/deregistering pins are also invoked by
|
|
the subsystem.
|
|
Notifications about status changes either of dpll device or a pin are
|
|
invoked in two ways:
|
|
|
|
- after successful change was requested on dpll subsystem, the subsystem
|
|
calls corresponding notification,
|
|
- requested by device driver with dpll_device_change_ntf() or
|
|
dpll_pin_change_ntf() when driver informs about the status change.
|
|
|
|
The device driver using dpll interface is not required to implement all
|
|
the callback operation. Nevertheless, there are few required to be
|
|
implemented.
|
|
Required dpll device level callback operations:
|
|
|
|
- ``.mode_get``,
|
|
- ``.lock_status_get``.
|
|
|
|
Required pin level callback operations:
|
|
|
|
- ``.state_on_dpll_get`` (pins registered with dpll device),
|
|
- ``.state_on_pin_get`` (pins registered with parent pin),
|
|
- ``.direction_get``.
|
|
|
|
Every other operation handler is checked for existence and
|
|
``-EOPNOTSUPP`` is returned in case of absence of specific handler.
|
|
|
|
The simplest implementation is in the OCP TimeCard driver. The ops
|
|
structures are defined like this:
|
|
|
|
.. code-block:: c
|
|
|
|
static const struct dpll_device_ops dpll_ops = {
|
|
.lock_status_get = ptp_ocp_dpll_lock_status_get,
|
|
.mode_get = ptp_ocp_dpll_mode_get,
|
|
.mode_supported = ptp_ocp_dpll_mode_supported,
|
|
};
|
|
|
|
static const struct dpll_pin_ops dpll_pins_ops = {
|
|
.frequency_get = ptp_ocp_dpll_frequency_get,
|
|
.frequency_set = ptp_ocp_dpll_frequency_set,
|
|
.direction_get = ptp_ocp_dpll_direction_get,
|
|
.direction_set = ptp_ocp_dpll_direction_set,
|
|
.state_on_dpll_get = ptp_ocp_dpll_state_get,
|
|
};
|
|
|
|
The registration part is then looks like this part:
|
|
|
|
.. code-block:: c
|
|
|
|
clkid = pci_get_dsn(pdev);
|
|
bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
|
|
if (IS_ERR(bp->dpll)) {
|
|
err = PTR_ERR(bp->dpll);
|
|
dev_err(&pdev->dev, "dpll_device_alloc failed\n");
|
|
goto out;
|
|
}
|
|
|
|
err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
|
|
if (err)
|
|
goto out;
|
|
|
|
for (i = 0; i < OCP_SMA_NUM; i++) {
|
|
bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
|
|
if (IS_ERR(bp->sma[i].dpll_pin)) {
|
|
err = PTR_ERR(bp->dpll);
|
|
goto out_dpll;
|
|
}
|
|
|
|
err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
|
|
&bp->sma[i]);
|
|
if (err) {
|
|
dpll_pin_put(bp->sma[i].dpll_pin);
|
|
goto out_dpll;
|
|
}
|
|
}
|
|
|
|
In the error path we have to rewind every allocation in the reverse order:
|
|
|
|
.. code-block:: c
|
|
|
|
while (i) {
|
|
--i;
|
|
dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
|
|
dpll_pin_put(bp->sma[i].dpll_pin);
|
|
}
|
|
dpll_device_put(bp->dpll);
|
|
|
|
More complex example can be found in Intel's ICE driver or nVidia's mlx5 driver.
|
|
|
|
SyncE enablement
|
|
================
|
|
For SyncE enablement it is required to allow control over dpll device
|
|
for a software application which monitors and configures the inputs of
|
|
dpll device in response to current state of a dpll device and its
|
|
inputs.
|
|
In such scenario, dpll device input signal shall be also configurable
|
|
to drive dpll with signal recovered from the PHY netdevice.
|
|
This is done by exposing a pin to the netdevice - attaching pin to the
|
|
netdevice itself with
|
|
``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``.
|
|
Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user
|
|
as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in
|
|
nested attribute ``IFLA_DPLL_PIN``.
|