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314 lines
8.8 KiB
C
314 lines
8.8 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <linux/dma-mapping.h>
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_connector.h"
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#include "nouveau_encoder.h"
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#include "nouveau_crtc.h"
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#define MEM_SYNC 0xe0000001
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#define MEM_VRAM 0xe0010000
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struct nvd0_display {
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struct nouveau_gpuobj *mem;
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struct {
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dma_addr_t handle;
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u32 *ptr;
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} evo[1];
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};
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static struct nvd0_display *
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nvd0_display(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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return dev_priv->engine.display.priv;
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}
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static int
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evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
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{
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int ret = 0;
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nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
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nv_wr32(dev, 0x610704 + (id * 0x10), data);
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nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
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if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
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ret = -EBUSY;
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nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
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return ret;
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}
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static u32 *
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evo_wait(struct drm_device *dev, int id, int nr)
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{
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struct nvd0_display *disp = nvd0_display(dev);
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u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
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if (put + nr >= (PAGE_SIZE / 4)) {
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disp->evo[id].ptr[put] = 0x20000000;
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nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
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if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
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NV_ERROR(dev, "evo %d dma stalled\n", id);
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return NULL;
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}
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put = 0;
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}
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return disp->evo[id].ptr + put;
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}
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static void
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evo_kick(u32 *push, struct drm_device *dev, int id)
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{
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struct nvd0_display *disp = nvd0_display(dev);
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nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
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}
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#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
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#define evo_data(p,d) *((p)++) = (d)
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/******************************************************************************
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* DAC
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*****************************************************************************/
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/******************************************************************************
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* SOR
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*****************************************************************************/
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/******************************************************************************
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* IRQ
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*****************************************************************************/
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static void
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nvd0_display_intr(struct drm_device *dev)
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{
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u32 intr = nv_rd32(dev, 0x610088);
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if (intr & 0x00000002) {
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u32 stat = nv_rd32(dev, 0x61009c);
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int chid = ffs(stat) - 1;
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if (chid >= 0) {
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u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
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u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
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u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
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NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
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"0x%08x 0x%08x\n",
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chid, (mthd & 0x0000ffc), data, mthd, unkn);
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nv_wr32(dev, 0x61009c, (1 << chid));
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nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
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}
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intr &= ~0x00000002;
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}
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if (intr & 0x01000000) {
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u32 stat = nv_rd32(dev, 0x6100bc);
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nv_wr32(dev, 0x6100bc, stat);
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intr &= ~0x01000000;
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}
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if (intr & 0x02000000) {
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u32 stat = nv_rd32(dev, 0x6108bc);
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nv_wr32(dev, 0x6108bc, stat);
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intr &= ~0x02000000;
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}
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if (intr)
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NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
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}
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/******************************************************************************
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* Init
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*****************************************************************************/
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static void
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nvd0_display_fini(struct drm_device *dev)
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{
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int i;
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/* fini cursors */
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for (i = 14; i >= 13; i--) {
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if (!(nv_rd32(dev, 0x610490 + (i * 0x10)) & 0x00000001))
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continue;
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nv_mask(dev, 0x610490 + (i * 0x10), 0x00000001, 0x00000000);
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nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00000000);
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nv_mask(dev, 0x610090, 1 << i, 0x00000000);
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nv_mask(dev, 0x6100a0, 1 << i, 0x00000000);
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}
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/* fini master */
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if (nv_rd32(dev, 0x610490) & 0x00000010) {
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nv_mask(dev, 0x610490, 0x00000010, 0x00000000);
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nv_mask(dev, 0x610490, 0x00000003, 0x00000000);
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nv_wait(dev, 0x610490, 0x80000000, 0x00000000);
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nv_mask(dev, 0x610090, 0x00000001, 0x00000000);
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nv_mask(dev, 0x6100a0, 0x00000001, 0x00000000);
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}
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}
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int
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nvd0_display_init(struct drm_device *dev)
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{
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struct nvd0_display *disp = nvd0_display(dev);
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u32 *push;
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int i;
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if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
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nv_wr32(dev, 0x6100ac, 0x00000100);
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nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
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if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
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NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
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nv_rd32(dev, 0x6194e8));
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return -EBUSY;
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}
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}
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nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
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/* init master */
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nv_wr32(dev, 0x610494, (disp->evo[0].handle >> 8) | 3);
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nv_wr32(dev, 0x610498, 0x00010000);
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nv_wr32(dev, 0x61049c, 0x00000001);
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nv_mask(dev, 0x610490, 0x00000010, 0x00000010);
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nv_wr32(dev, 0x640000, 0x00000000);
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nv_wr32(dev, 0x610490, 0x01000013);
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if (!nv_wait(dev, 0x610490, 0x80000000, 0x00000000)) {
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NV_ERROR(dev, "PDISP: master 0x%08x\n",
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nv_rd32(dev, 0x610490));
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return -EBUSY;
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}
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nv_mask(dev, 0x610090, 0x00000001, 0x00000001);
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nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001);
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/* init cursors */
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for (i = 13; i <= 14; i++) {
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nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001);
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if (!nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00010000)) {
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NV_ERROR(dev, "PDISP: curs%d 0x%08x\n", i,
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nv_rd32(dev, 0x610490 + (i * 0x10)));
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return -EBUSY;
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}
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nv_mask(dev, 0x610090, 1 << i, 1 << i);
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nv_mask(dev, 0x6100a0, 1 << i, 1 << i);
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}
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push = evo_wait(dev, 0, 32);
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if (!push)
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return -EBUSY;
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evo_mthd(push, 0x0088, 1);
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evo_data(push, MEM_SYNC);
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x80000000);
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evo_mthd(push, 0x008c, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, dev, 0);
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return 0;
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}
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void
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nvd0_display_destroy(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvd0_display *disp = nvd0_display(dev);
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struct pci_dev *pdev = dev->pdev;
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nvd0_display_fini(dev);
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pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
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nouveau_gpuobj_ref(NULL, &disp->mem);
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nouveau_irq_unregister(dev, 26);
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dev_priv->engine.display.priv = NULL;
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kfree(disp);
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}
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int
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nvd0_display_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct pci_dev *pdev = dev->pdev;
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struct nvd0_display *disp;
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int ret;
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disp = kzalloc(sizeof(*disp), GFP_KERNEL);
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if (!disp)
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return -ENOMEM;
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dev_priv->engine.display.priv = disp;
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/* setup interrupt handling */
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nouveau_irq_register(dev, 26, nvd0_display_intr);
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/* hash table and dma objects for the memory areas we care about */
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ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
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NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
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if (ret)
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goto out;
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nv_wo32(disp->mem, 0x1000, 0x00000049);
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nv_wo32(disp->mem, 0x1004, (disp->mem->vinst + 0x2000) >> 8);
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nv_wo32(disp->mem, 0x1008, (disp->mem->vinst + 0x2fff) >> 8);
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nv_wo32(disp->mem, 0x100c, 0x00000000);
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nv_wo32(disp->mem, 0x1010, 0x00000000);
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nv_wo32(disp->mem, 0x1014, 0x00000000);
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nv_wo32(disp->mem, 0x0000, MEM_SYNC);
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nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
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nv_wo32(disp->mem, 0x1020, 0x00000009);
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nv_wo32(disp->mem, 0x1024, 0x00000000);
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nv_wo32(disp->mem, 0x1028, (dev_priv->vram_size - 1) >> 8);
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nv_wo32(disp->mem, 0x102c, 0x00000000);
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nv_wo32(disp->mem, 0x1030, 0x00000000);
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nv_wo32(disp->mem, 0x1034, 0x00000000);
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nv_wo32(disp->mem, 0x0008, MEM_VRAM);
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nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
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pinstmem->flush(dev);
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/* push buffers for evo channels */
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disp->evo[0].ptr =
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pci_alloc_consistent(pdev, PAGE_SIZE, &disp->evo[0].handle);
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if (!disp->evo[0].ptr) {
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ret = -ENOMEM;
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goto out;
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}
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ret = nvd0_display_init(dev);
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if (ret)
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goto out;
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out:
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if (ret)
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nvd0_display_destroy(dev);
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return ret;
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}
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