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ae1dd17dae
Use job ring register map, in place of controller register map to access page 0 registers, as access to the controller register map is not permitted. Signed-off-by: Horia GeantA <horia.geanta@nxp.com> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Varun Sethi <v.sethi@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
264 lines
5.6 KiB
C
264 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* caam - Freescale FSL CAAM support for hw_random
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*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2018-2019, 2023 NXP
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*
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* Based on caamalg.c crypto API driver.
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*
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*/
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#include <linux/hw_random.h>
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#include <linux/completion.h>
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#include <linux/atomic.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/kfifo.h>
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#include "compat.h"
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#include "regs.h"
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#include "intern.h"
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#include "desc_constr.h"
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#include "jr.h"
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#include "error.h"
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#define CAAM_RNG_MAX_FIFO_STORE_SIZE 16
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/*
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* Length of used descriptors, see caam_init_desc()
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*/
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#define CAAM_RNG_DESC_LEN (CAAM_CMD_SZ + \
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CAAM_CMD_SZ + \
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CAAM_CMD_SZ + CAAM_PTR_SZ_MAX)
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/* rng per-device context */
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struct caam_rng_ctx {
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struct hwrng rng;
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struct device *jrdev;
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struct device *ctrldev;
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void *desc_async;
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void *desc_sync;
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struct work_struct worker;
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struct kfifo fifo;
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};
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struct caam_rng_job_ctx {
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struct completion *done;
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int *err;
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};
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static struct caam_rng_ctx *to_caam_rng_ctx(struct hwrng *r)
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{
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return (struct caam_rng_ctx *)r->priv;
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}
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static void caam_rng_done(struct device *jrdev, u32 *desc, u32 err,
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void *context)
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{
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struct caam_rng_job_ctx *jctx = context;
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if (err)
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*jctx->err = caam_jr_strstatus(jrdev, err);
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complete(jctx->done);
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}
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static u32 *caam_init_desc(u32 *desc, dma_addr_t dst_dma)
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{
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init_job_desc(desc, 0); /* + 1 cmd_sz */
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/* Generate random bytes: + 1 cmd_sz */
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append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG |
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OP_ALG_PR_ON);
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/* Store bytes: + 1 cmd_sz + caam_ptr_sz */
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append_fifo_store(desc, dst_dma,
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CAAM_RNG_MAX_FIFO_STORE_SIZE, FIFOST_TYPE_RNGSTORE);
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print_hex_dump_debug("rng job desc@: ", DUMP_PREFIX_ADDRESS,
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16, 4, desc, desc_bytes(desc), 1);
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return desc;
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}
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static int caam_rng_read_one(struct device *jrdev,
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void *dst, int len,
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void *desc,
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struct completion *done)
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{
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dma_addr_t dst_dma;
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int err, ret = 0;
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struct caam_rng_job_ctx jctx = {
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.done = done,
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.err = &ret,
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};
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len = CAAM_RNG_MAX_FIFO_STORE_SIZE;
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dst_dma = dma_map_single(jrdev, dst, len, DMA_FROM_DEVICE);
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if (dma_mapping_error(jrdev, dst_dma)) {
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dev_err(jrdev, "unable to map destination memory\n");
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return -ENOMEM;
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}
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init_completion(done);
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err = caam_jr_enqueue(jrdev,
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caam_init_desc(desc, dst_dma),
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caam_rng_done, &jctx);
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if (err == -EINPROGRESS) {
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wait_for_completion(done);
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err = 0;
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}
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dma_unmap_single(jrdev, dst_dma, len, DMA_FROM_DEVICE);
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return err ?: (ret ?: len);
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}
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static void caam_rng_fill_async(struct caam_rng_ctx *ctx)
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{
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struct scatterlist sg[1];
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struct completion done;
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int len, nents;
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sg_init_table(sg, ARRAY_SIZE(sg));
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nents = kfifo_dma_in_prepare(&ctx->fifo, sg, ARRAY_SIZE(sg),
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CAAM_RNG_MAX_FIFO_STORE_SIZE);
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if (!nents)
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return;
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len = caam_rng_read_one(ctx->jrdev, sg_virt(&sg[0]),
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sg[0].length,
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ctx->desc_async,
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&done);
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if (len < 0)
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return;
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kfifo_dma_in_finish(&ctx->fifo, len);
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}
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static void caam_rng_worker(struct work_struct *work)
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{
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struct caam_rng_ctx *ctx = container_of(work, struct caam_rng_ctx,
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worker);
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caam_rng_fill_async(ctx);
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}
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static int caam_read(struct hwrng *rng, void *dst, size_t max, bool wait)
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{
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struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng);
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int out;
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if (wait) {
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struct completion done;
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return caam_rng_read_one(ctx->jrdev, dst, max,
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ctx->desc_sync, &done);
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}
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out = kfifo_out(&ctx->fifo, dst, max);
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if (kfifo_is_empty(&ctx->fifo))
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schedule_work(&ctx->worker);
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return out;
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}
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static void caam_cleanup(struct hwrng *rng)
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{
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struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng);
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flush_work(&ctx->worker);
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caam_jr_free(ctx->jrdev);
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kfifo_free(&ctx->fifo);
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}
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static int caam_init(struct hwrng *rng)
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{
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struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng);
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int err;
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ctx->desc_sync = devm_kzalloc(ctx->ctrldev, CAAM_RNG_DESC_LEN,
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GFP_KERNEL);
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if (!ctx->desc_sync)
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return -ENOMEM;
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ctx->desc_async = devm_kzalloc(ctx->ctrldev, CAAM_RNG_DESC_LEN,
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GFP_KERNEL);
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if (!ctx->desc_async)
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return -ENOMEM;
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if (kfifo_alloc(&ctx->fifo, ALIGN(CAAM_RNG_MAX_FIFO_STORE_SIZE,
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dma_get_cache_alignment()),
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GFP_KERNEL))
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return -ENOMEM;
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INIT_WORK(&ctx->worker, caam_rng_worker);
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ctx->jrdev = caam_jr_alloc();
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err = PTR_ERR_OR_ZERO(ctx->jrdev);
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if (err) {
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kfifo_free(&ctx->fifo);
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pr_err("Job Ring Device allocation for transform failed\n");
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return err;
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}
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/*
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* Fill async buffer to have early randomness data for
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* hw_random
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*/
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caam_rng_fill_async(ctx);
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return 0;
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}
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int caam_rng_init(struct device *ctrldev);
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void caam_rng_exit(struct device *ctrldev)
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{
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devres_release_group(ctrldev, caam_rng_init);
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}
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int caam_rng_init(struct device *ctrldev)
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{
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struct caam_rng_ctx *ctx;
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u32 rng_inst;
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struct caam_drv_private *priv = dev_get_drvdata(ctrldev);
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int ret;
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/* Check for an instantiated RNG before registration */
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if (priv->era < 10)
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rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
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CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
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else
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rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK;
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if (!rng_inst)
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return 0;
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if (!devres_open_group(ctrldev, caam_rng_init, GFP_KERNEL))
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return -ENOMEM;
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ctx = devm_kzalloc(ctrldev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->ctrldev = ctrldev;
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ctx->rng.name = "rng-caam";
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ctx->rng.init = caam_init;
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ctx->rng.cleanup = caam_cleanup;
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ctx->rng.read = caam_read;
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ctx->rng.priv = (unsigned long)ctx;
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dev_info(ctrldev, "registering rng-caam\n");
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ret = devm_hwrng_register(ctrldev, &ctx->rng);
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if (ret) {
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caam_rng_exit(ctrldev);
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return ret;
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}
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devres_close_group(ctrldev, caam_rng_init);
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return 0;
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}
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