Adrián Larumbe 7ed40ff1d1 drm/bridge: dw-hdmi: change YUV420 selection logic at clock setup ... Right now clocking value selection code is prioritising RGB, YUV444 modes over YUV420 for HDMI2 sinks. However, because of the bus format selection procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always be picked during the drm bridge chain check stage. Later on dw_hdmi_setup will configure a colour space based on the bus format that doesn't match the pixel value we had calculated as described above. Fix it by bringing back dw-hdmi bus format check when picking the right pixel clock. Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/6230bfae2cd97cf6527fc62ba5c850464919ccf8.1687702042.git.adrian.larumbe@collabora.com		2023-06-27 09:51:31 +02:00
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analogix_dp.h	drm/bridge: analogix_dp: Split bind() into probe() and real bind()	2020-04-09 10:29:35 +02:00
dw_hdmi.h	drm/bridge: dw-hdmi: change YUV420 selection logic at clock setup	2023-06-27 09:51:31 +02:00
dw_mipi_dsi.h	drm/bridge/synopsys: dsi: extend the prototype of mode_valid()	2022-01-04 12:53:59 +01:00
mhl.h	drm/bridge/mhl.h: Replace zero-length array with flexible-array member	2020-03-06 11:52:01 +01:00
samsung-dsim.h	drm: bridge: samsung-dsim: Dynamically configure DPHY timing	2023-05-26 09:20:41 +02:00