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09da89abe3
On Family 17h (Ryzen) devices, the WatchdogTmrEn bit of PmDecodeEn not only enables watchdog memory decoding at 0xfeb00000, it also enables the watchdog hardware itself. Use this information to enable the watchdog if it is not already enabled. Cc: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20200910163109.235136-2-linux@roeck-us.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
507 lines
13 KiB
C
507 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* sp5100_tco : TCO timer driver for sp5100 chipsets
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*
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* (c) Copyright 2009 Google Inc., All Rights Reserved.
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*
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* Based on i8xx_tco.c:
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* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
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* Reserved.
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* https://www.kernelconcepts.de
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*
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* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
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* AMD Publication 45482 "AMD SB800-Series Southbridges Register
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* Reference Guide"
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* AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
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* for AMD Family 16h Models 00h-0Fh Processors"
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* AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
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* AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
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* for AMD Family 16h Models 30h-3Fh Processors"
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* AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
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* for AMD Family 17h Model 18h, Revision B1
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* Processors (PUB)
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* AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
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* for AMD Family 17h Model 20h, Revision A1
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* Processors (PUB)
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*/
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/*
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* Includes, defines, variables, module parameters, ...
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#include "sp5100_tco.h"
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#define TCO_DRIVER_NAME "sp5100-tco"
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/* internal variables */
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enum tco_reg_layout {
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sp5100, sb800, efch
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};
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struct sp5100_tco {
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struct watchdog_device wdd;
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void __iomem *tcobase;
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enum tco_reg_layout tco_reg_layout;
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};
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/* the watchdog platform device */
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static struct platform_device *sp5100_tco_platform_device;
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/* the associated PCI device */
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static struct pci_dev *sp5100_tco_pci;
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/* module parameters */
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#define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
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static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
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__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
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" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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/*
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* Some TCO specific functions
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*/
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static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
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{
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if (dev->vendor == PCI_VENDOR_ID_ATI &&
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dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
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dev->revision < 0x40) {
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return sp5100;
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} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
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((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
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dev->revision >= 0x41) ||
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(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
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dev->revision >= 0x49))) {
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return efch;
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}
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return sb800;
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}
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static int tco_timer_start(struct watchdog_device *wdd)
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{
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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u32 val;
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val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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val |= SP5100_WDT_START_STOP_BIT;
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writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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return 0;
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}
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static int tco_timer_stop(struct watchdog_device *wdd)
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{
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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u32 val;
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val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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val &= ~SP5100_WDT_START_STOP_BIT;
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writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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return 0;
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}
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static int tco_timer_ping(struct watchdog_device *wdd)
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{
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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u32 val;
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val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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val |= SP5100_WDT_TRIGGER_BIT;
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writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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return 0;
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}
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static int tco_timer_set_timeout(struct watchdog_device *wdd,
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unsigned int t)
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{
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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/* Write new heartbeat to watchdog */
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writel(t, SP5100_WDT_COUNT(tco->tcobase));
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wdd->timeout = t;
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return 0;
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}
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static u8 sp5100_tco_read_pm_reg8(u8 index)
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{
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outb(index, SP5100_IO_PM_INDEX_REG);
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return inb(SP5100_IO_PM_DATA_REG);
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}
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static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
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{
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u8 val;
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outb(index, SP5100_IO_PM_INDEX_REG);
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val = inb(SP5100_IO_PM_DATA_REG);
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val &= reset;
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val |= set;
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outb(val, SP5100_IO_PM_DATA_REG);
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}
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static void tco_timer_enable(struct sp5100_tco *tco)
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{
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u32 val;
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switch (tco->tco_reg_layout) {
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case sb800:
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/* For SB800 or later */
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/* Set the Watchdog timer resolution to 1 sec */
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sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
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0xff, SB800_PM_WATCHDOG_SECOND_RES);
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/* Enable watchdog decode bit and watchdog timer */
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sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
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~SB800_PM_WATCHDOG_DISABLE,
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SB800_PCI_WATCHDOG_DECODE_EN);
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break;
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case sp5100:
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/* For SP5100 or SB7x0 */
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/* Enable watchdog decode bit */
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pci_read_config_dword(sp5100_tco_pci,
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SP5100_PCI_WATCHDOG_MISC_REG,
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&val);
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val |= SP5100_PCI_WATCHDOG_DECODE_EN;
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pci_write_config_dword(sp5100_tco_pci,
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SP5100_PCI_WATCHDOG_MISC_REG,
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val);
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/* Enable Watchdog timer and set the resolution to 1 sec */
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sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
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~SP5100_PM_WATCHDOG_DISABLE,
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SP5100_PM_WATCHDOG_SECOND_RES);
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break;
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case efch:
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/* Set the Watchdog timer resolution to 1 sec and enable */
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sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
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~EFCH_PM_WATCHDOG_DISABLE,
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EFCH_PM_DECODEEN_SECOND_RES);
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break;
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}
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}
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static u32 sp5100_tco_read_pm_reg32(u8 index)
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{
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u32 val = 0;
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int i;
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for (i = 3; i >= 0; i--)
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val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
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return val;
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}
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static int sp5100_tco_setupdevice(struct device *dev,
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struct watchdog_device *wdd)
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{
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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const char *dev_name;
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u32 mmio_addr = 0, val;
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int ret;
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/* Request the IO ports used by this driver */
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if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
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SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
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dev_err(dev, "I/O address 0x%04x already in use\n",
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SP5100_IO_PM_INDEX_REG);
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return -EBUSY;
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}
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/*
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* Determine type of southbridge chipset.
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*/
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switch (tco->tco_reg_layout) {
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case sp5100:
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dev_name = SP5100_DEVNAME;
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mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
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0xfffffff8;
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break;
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case sb800:
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dev_name = SB800_DEVNAME;
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mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
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0xfffffff8;
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break;
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case efch:
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dev_name = SB800_DEVNAME;
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/*
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* On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of
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* EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory
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* region, it also enables the watchdog itself.
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*/
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if (boot_cpu_data.x86 == 0x17) {
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val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
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if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
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sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,
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EFCH_PM_DECODEEN_WDT_TMREN);
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}
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}
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val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
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if (val & EFCH_PM_DECODEEN_WDT_TMREN)
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mmio_addr = EFCH_PM_WDT_ADDR;
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break;
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default:
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return -ENODEV;
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}
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/* Check MMIO address conflict */
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if (!mmio_addr ||
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!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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if (mmio_addr)
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dev_dbg(dev, "MMIO address 0x%08x already in use\n",
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mmio_addr);
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switch (tco->tco_reg_layout) {
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case sp5100:
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/*
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* Secondly, Find the watchdog timer MMIO address
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* from SBResource_MMIO register.
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*/
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/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
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pci_read_config_dword(sp5100_tco_pci,
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SP5100_SB_RESOURCE_MMIO_BASE,
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&mmio_addr);
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if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
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SB800_ACPI_MMIO_SEL)) !=
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SB800_ACPI_MMIO_DECODE_EN) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr &= ~0xFFF;
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mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
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break;
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case sb800:
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/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
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mmio_addr =
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sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
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if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
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SB800_ACPI_MMIO_SEL)) !=
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SB800_ACPI_MMIO_DECODE_EN) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr &= ~0xFFF;
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mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
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break;
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case efch:
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val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
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if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
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EFCH_PM_ACPI_MMIO_WDT_OFFSET;
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break;
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}
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dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
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mmio_addr);
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if (!devm_request_mem_region(dev, mmio_addr,
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SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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dev_dbg(dev, "MMIO address 0x%08x already in use\n",
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mmio_addr);
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ret = -EBUSY;
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goto unreg_region;
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}
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}
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tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
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if (!tco->tcobase) {
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dev_err(dev, "failed to get tcobase address\n");
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ret = -ENOMEM;
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goto unreg_region;
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}
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dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
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/* Setup the watchdog timer */
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tco_timer_enable(tco);
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val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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if (val & SP5100_WDT_DISABLED) {
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dev_err(dev, "Watchdog hardware is disabled\n");
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ret = -ENODEV;
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goto unreg_region;
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}
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/*
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* Save WatchDogFired status, because WatchDogFired flag is
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* cleared here.
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*/
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if (val & SP5100_WDT_FIRED)
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wdd->bootstatus = WDIOF_CARDRESET;
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/* Set watchdog action to reset the system */
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val &= ~SP5100_WDT_ACTION_RESET;
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writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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/* Set a reasonable heartbeat before we stop the timer */
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tco_timer_set_timeout(wdd, wdd->timeout);
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/*
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* Stop the TCO before we change anything so we don't race with
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* a zeroed timer.
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*/
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tco_timer_stop(wdd);
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release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
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return 0;
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unreg_region:
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release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
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return ret;
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}
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static struct watchdog_info sp5100_tco_wdt_info = {
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.identity = "SP5100 TCO timer",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops sp5100_tco_wdt_ops = {
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.owner = THIS_MODULE,
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.start = tco_timer_start,
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.stop = tco_timer_stop,
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.ping = tco_timer_ping,
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.set_timeout = tco_timer_set_timeout,
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};
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static int sp5100_tco_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct watchdog_device *wdd;
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struct sp5100_tco *tco;
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int ret;
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tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
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if (!tco)
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return -ENOMEM;
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tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
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wdd = &tco->wdd;
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wdd->parent = dev;
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wdd->info = &sp5100_tco_wdt_info;
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wdd->ops = &sp5100_tco_wdt_ops;
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wdd->timeout = WATCHDOG_HEARTBEAT;
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wdd->min_timeout = 1;
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wdd->max_timeout = 0xffff;
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watchdog_init_timeout(wdd, heartbeat, NULL);
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watchdog_set_nowayout(wdd, nowayout);
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watchdog_stop_on_reboot(wdd);
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watchdog_stop_on_unregister(wdd);
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watchdog_set_drvdata(wdd, tco);
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ret = sp5100_tco_setupdevice(dev, wdd);
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if (ret)
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return ret;
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ret = devm_watchdog_register_device(dev, wdd);
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if (ret)
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return ret;
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/* Show module parameters */
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dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
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wdd->timeout, nowayout);
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return 0;
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}
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static struct platform_driver sp5100_tco_driver = {
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.probe = sp5100_tco_probe,
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.driver = {
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.name = TCO_DRIVER_NAME,
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},
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};
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because someone else might
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* want to register another driver on the same PCI id.
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*/
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static const struct pci_device_id sp5100_tco_pci_tbl[] = {
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
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PCI_ANY_ID, },
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{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
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PCI_ANY_ID, },
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{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
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PCI_ANY_ID, },
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{ 0, }, /* End of list */
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};
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MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
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static int __init sp5100_tco_init(void)
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{
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struct pci_dev *dev = NULL;
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int err;
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/* Match the PCI device */
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for_each_pci_dev(dev) {
|
||
if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
|
||
sp5100_tco_pci = dev;
|
||
break;
|
||
}
|
||
}
|
||
|
||
if (!sp5100_tco_pci)
|
||
return -ENODEV;
|
||
|
||
pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
|
||
|
||
err = platform_driver_register(&sp5100_tco_driver);
|
||
if (err)
|
||
return err;
|
||
|
||
sp5100_tco_platform_device =
|
||
platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
|
||
if (IS_ERR(sp5100_tco_platform_device)) {
|
||
err = PTR_ERR(sp5100_tco_platform_device);
|
||
goto unreg_platform_driver;
|
||
}
|
||
|
||
return 0;
|
||
|
||
unreg_platform_driver:
|
||
platform_driver_unregister(&sp5100_tco_driver);
|
||
return err;
|
||
}
|
||
|
||
static void __exit sp5100_tco_exit(void)
|
||
{
|
||
platform_device_unregister(sp5100_tco_platform_device);
|
||
platform_driver_unregister(&sp5100_tco_driver);
|
||
}
|
||
|
||
module_init(sp5100_tco_init);
|
||
module_exit(sp5100_tco_exit);
|
||
|
||
MODULE_AUTHOR("Priyanka Gupta");
|
||
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
|
||
MODULE_LICENSE("GPL");
|