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cb6b0a393c
Some Amlogic boards store the Ethernet MAC address inside the eFuse. The Ethernet MAC address uses 6 bytes. The existing logic in meson_mx_efuse_read() would write beyond the end of the data buffer when trying to read data with a size that is not aligned to word_size (4 bytes on Meson8, Meson8b and Meson8m2). Calculate the remaining data to copy inside meson_mx_efuse_read() so reading 6 bytes doesn't write beyond the end of the data buffer. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20190818093345.29647-5-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
247 lines
6.6 KiB
C
247 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Amlogic Meson6, Meson8 and Meson8b eFuse Driver
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*
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* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#define MESON_MX_EFUSE_CNTL1 0x04
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#define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27)
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#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26)
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#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25)
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#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24)
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#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)
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#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14)
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#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13)
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#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12)
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#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11)
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#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)
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#define MESON_MX_EFUSE_CNTL2 0x08
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#define MESON_MX_EFUSE_CNTL4 0x10
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#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10)
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struct meson_mx_efuse_platform_data {
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const char *name;
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unsigned int word_size;
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};
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struct meson_mx_efuse {
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void __iomem *base;
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struct clk *core_clk;
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struct nvmem_device *nvmem;
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struct nvmem_config config;
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};
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static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
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u32 mask, u32 set)
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{
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u32 data;
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data = readl(efuse->base + reg);
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data &= ~mask;
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data |= (set & mask);
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writel(data, efuse->base + reg);
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}
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static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
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{
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int err;
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err = clk_prepare_enable(efuse->core_clk);
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if (err)
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return err;
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/* power up the efuse */
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
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MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);
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return 0;
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}
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static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
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{
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_PD_ENABLE,
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MESON_MX_EFUSE_CNTL1_PD_ENABLE);
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clk_disable_unprepare(efuse->core_clk);
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}
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static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
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unsigned int addr, u32 *value)
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{
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int err;
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u32 regval;
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/* write the address to read */
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regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);
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/* inform the hardware that we changed the address */
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
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MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);
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/* start the read process */
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
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MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);
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/*
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* perform a dummy read to ensure that the HW has the RD_BUSY bit set
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* when polling for the status below.
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*/
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readl(efuse->base + MESON_MX_EFUSE_CNTL1);
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err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
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regval,
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(!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
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1, 1000);
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if (err) {
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dev_err(efuse->config.dev,
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"Timeout while reading efuse address %u\n", addr);
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return err;
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}
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*value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
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return 0;
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}
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static int meson_mx_efuse_read(void *context, unsigned int offset,
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void *buf, size_t bytes)
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{
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struct meson_mx_efuse *efuse = context;
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u32 tmp;
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int err, i, addr;
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err = meson_mx_efuse_hw_enable(efuse);
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if (err)
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return err;
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
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MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);
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for (i = 0; i < bytes; i += efuse->config.word_size) {
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addr = (offset + i) / efuse->config.word_size;
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err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
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if (err)
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break;
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memcpy(buf + i, &tmp,
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min_t(size_t, bytes - i, efuse->config.word_size));
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}
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meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
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MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);
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meson_mx_efuse_hw_disable(efuse);
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return err;
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}
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static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
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.name = "meson6-efuse",
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.word_size = 1,
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};
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static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
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.name = "meson8-efuse",
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.word_size = 4,
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};
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static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
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.name = "meson8b-efuse",
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.word_size = 4,
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};
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static const struct of_device_id meson_mx_efuse_match[] = {
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{ .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
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{ .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
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{ .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);
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static int meson_mx_efuse_probe(struct platform_device *pdev)
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{
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const struct meson_mx_efuse_platform_data *drvdata;
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struct meson_mx_efuse *efuse;
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struct resource *res;
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drvdata = of_device_get_match_data(&pdev->dev);
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if (!drvdata)
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return -EINVAL;
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efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
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if (!efuse)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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efuse->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(efuse->base))
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return PTR_ERR(efuse->base);
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efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name,
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GFP_KERNEL);
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efuse->config.owner = THIS_MODULE;
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efuse->config.dev = &pdev->dev;
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efuse->config.priv = efuse;
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efuse->config.stride = drvdata->word_size;
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efuse->config.word_size = drvdata->word_size;
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efuse->config.size = SZ_512;
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efuse->config.read_only = true;
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efuse->config.reg_read = meson_mx_efuse_read;
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efuse->core_clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(efuse->core_clk)) {
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dev_err(&pdev->dev, "Failed to get core clock\n");
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return PTR_ERR(efuse->core_clk);
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}
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efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
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return PTR_ERR_OR_ZERO(efuse->nvmem);
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}
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static struct platform_driver meson_mx_efuse_driver = {
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.probe = meson_mx_efuse_probe,
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.driver = {
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.name = "meson-mx-efuse",
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.of_match_table = meson_mx_efuse_match,
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},
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};
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module_platform_driver(meson_mx_efuse_driver);
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
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MODULE_LICENSE("GPL v2");
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