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183747ab52
This patch adds missing MODULE_DEVICE_TABLE definition which generates
correct modalias for automatic loading of this cpufreq driver when it is
compiled as an external module.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: ab0ea257fc
("cpufreq: st: Provide runtime initialised driver for ST's platforms")
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
311 lines
7.3 KiB
C
311 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Match running platform with pre-defined OPP values for CPUFreq
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*
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* Author: Ajit Pal Singh <ajitpal.singh@st.com>
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* Lee Jones <lee.jones@linaro.org>
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*
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* Copyright (C) 2015 STMicroelectronics (R&D) Limited
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*/
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#include <linux/cpu.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pm_opp.h>
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#include <linux/regmap.h>
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#define VERSION_ELEMENTS 3
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#define MAX_PCODE_NAME_LEN 7
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#define VERSION_SHIFT 28
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#define HW_INFO_INDEX 1
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#define MAJOR_ID_INDEX 1
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#define MINOR_ID_INDEX 2
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/*
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* Only match on "suitable for ALL versions" entries
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*
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* This will be used with the BIT() macro. It sets the
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* top bit of a 32bit value and is equal to 0x80000000.
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*/
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#define DEFAULT_VERSION 31
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enum {
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PCODE = 0,
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SUBSTRATE,
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DVFS_MAX_REGFIELDS,
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};
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/**
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* struct sti_cpufreq_ddata - ST CPUFreq Driver Data
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*
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* @cpu: CPU's OF node
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* @syscfg_eng: Engineering Syscon register map
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* @syscfg: Syscon register map
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*/
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static struct sti_cpufreq_ddata {
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struct device *cpu;
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struct regmap *syscfg_eng;
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struct regmap *syscfg;
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} ddata;
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static int sti_cpufreq_fetch_major(void) {
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struct device_node *np = ddata.cpu->of_node;
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struct device *dev = ddata.cpu;
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unsigned int major_offset;
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unsigned int socid;
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int ret;
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ret = of_property_read_u32_index(np, "st,syscfg",
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MAJOR_ID_INDEX, &major_offset);
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if (ret) {
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dev_err(dev, "No major number offset provided in %pOF [%d]\n",
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np, ret);
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return ret;
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}
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ret = regmap_read(ddata.syscfg, major_offset, &socid);
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if (ret) {
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dev_err(dev, "Failed to read major number from syscon [%d]\n",
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ret);
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return ret;
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}
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return ((socid >> VERSION_SHIFT) & 0xf) + 1;
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}
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static int sti_cpufreq_fetch_minor(void)
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{
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struct device *dev = ddata.cpu;
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struct device_node *np = dev->of_node;
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unsigned int minor_offset;
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unsigned int minid;
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int ret;
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ret = of_property_read_u32_index(np, "st,syscfg-eng",
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MINOR_ID_INDEX, &minor_offset);
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if (ret) {
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dev_err(dev,
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"No minor number offset provided %pOF [%d]\n",
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np, ret);
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return ret;
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}
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ret = regmap_read(ddata.syscfg_eng, minor_offset, &minid);
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if (ret) {
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dev_err(dev,
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"Failed to read the minor number from syscon [%d]\n",
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ret);
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return ret;
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}
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return minid & 0xf;
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}
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static int sti_cpufreq_fetch_regmap_field(const struct reg_field *reg_fields,
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int hw_info_offset, int field)
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{
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struct regmap_field *regmap_field;
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struct reg_field reg_field = reg_fields[field];
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struct device *dev = ddata.cpu;
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unsigned int value;
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int ret;
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reg_field.reg = hw_info_offset;
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regmap_field = devm_regmap_field_alloc(dev,
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ddata.syscfg_eng,
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reg_field);
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if (IS_ERR(regmap_field)) {
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dev_err(dev, "Failed to allocate reg field\n");
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return PTR_ERR(regmap_field);
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}
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ret = regmap_field_read(regmap_field, &value);
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if (ret) {
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dev_err(dev, "Failed to read %s code\n",
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field ? "SUBSTRATE" : "PCODE");
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return ret;
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}
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return value;
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}
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static const struct reg_field sti_stih407_dvfs_regfields[DVFS_MAX_REGFIELDS] = {
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[PCODE] = REG_FIELD(0, 16, 19),
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[SUBSTRATE] = REG_FIELD(0, 0, 2),
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};
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static const struct reg_field *sti_cpufreq_match(void)
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{
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if (of_machine_is_compatible("st,stih407") ||
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of_machine_is_compatible("st,stih410") ||
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of_machine_is_compatible("st,stih418"))
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return sti_stih407_dvfs_regfields;
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return NULL;
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}
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static int sti_cpufreq_set_opp_info(void)
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{
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struct device *dev = ddata.cpu;
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struct device_node *np = dev->of_node;
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const struct reg_field *reg_fields;
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unsigned int hw_info_offset;
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unsigned int version[VERSION_ELEMENTS];
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int pcode, substrate, major, minor;
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int ret;
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char name[MAX_PCODE_NAME_LEN];
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struct opp_table *opp_table;
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reg_fields = sti_cpufreq_match();
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if (!reg_fields) {
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dev_err(dev, "This SoC doesn't support voltage scaling\n");
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return -ENODEV;
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}
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ret = of_property_read_u32_index(np, "st,syscfg-eng",
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HW_INFO_INDEX, &hw_info_offset);
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if (ret) {
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dev_warn(dev, "Failed to read HW info offset from DT\n");
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substrate = DEFAULT_VERSION;
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pcode = 0;
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goto use_defaults;
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}
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pcode = sti_cpufreq_fetch_regmap_field(reg_fields,
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hw_info_offset,
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PCODE);
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if (pcode < 0) {
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dev_warn(dev, "Failed to obtain process code\n");
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/* Use default pcode */
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pcode = 0;
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}
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substrate = sti_cpufreq_fetch_regmap_field(reg_fields,
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hw_info_offset,
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SUBSTRATE);
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if (substrate) {
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dev_warn(dev, "Failed to obtain substrate code\n");
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/* Use default substrate */
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substrate = DEFAULT_VERSION;
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}
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use_defaults:
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major = sti_cpufreq_fetch_major();
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if (major < 0) {
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dev_err(dev, "Failed to obtain major version\n");
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/* Use default major number */
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major = DEFAULT_VERSION;
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}
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minor = sti_cpufreq_fetch_minor();
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if (minor < 0) {
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dev_err(dev, "Failed to obtain minor version\n");
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/* Use default minor number */
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minor = DEFAULT_VERSION;
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}
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snprintf(name, MAX_PCODE_NAME_LEN, "pcode%d", pcode);
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opp_table = dev_pm_opp_set_prop_name(dev, name);
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if (IS_ERR(opp_table)) {
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dev_err(dev, "Failed to set prop name\n");
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return PTR_ERR(opp_table);
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}
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version[0] = BIT(major);
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version[1] = BIT(minor);
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version[2] = BIT(substrate);
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opp_table = dev_pm_opp_set_supported_hw(dev, version, VERSION_ELEMENTS);
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if (IS_ERR(opp_table)) {
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dev_err(dev, "Failed to set supported hardware\n");
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ret = PTR_ERR(opp_table);
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goto err_put_prop_name;
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}
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dev_dbg(dev, "pcode: %d major: %d minor: %d substrate: %d\n",
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pcode, major, minor, substrate);
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dev_dbg(dev, "version[0]: %x version[1]: %x version[2]: %x\n",
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version[0], version[1], version[2]);
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return 0;
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err_put_prop_name:
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dev_pm_opp_put_prop_name(opp_table);
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return ret;
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}
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static int sti_cpufreq_fetch_syscon_registers(void)
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{
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struct device *dev = ddata.cpu;
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struct device_node *np = dev->of_node;
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ddata.syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
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if (IS_ERR(ddata.syscfg)) {
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dev_err(dev, "\"st,syscfg\" not supplied\n");
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return PTR_ERR(ddata.syscfg);
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}
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ddata.syscfg_eng = syscon_regmap_lookup_by_phandle(np, "st,syscfg-eng");
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if (IS_ERR(ddata.syscfg_eng)) {
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dev_err(dev, "\"st,syscfg-eng\" not supplied\n");
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return PTR_ERR(ddata.syscfg_eng);
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}
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return 0;
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}
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static int sti_cpufreq_init(void)
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{
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int ret;
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if ((!of_machine_is_compatible("st,stih407")) &&
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(!of_machine_is_compatible("st,stih410")) &&
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(!of_machine_is_compatible("st,stih418")))
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return -ENODEV;
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ddata.cpu = get_cpu_device(0);
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if (!ddata.cpu) {
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dev_err(ddata.cpu, "Failed to get device for CPU0\n");
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goto skip_voltage_scaling;
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}
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if (!of_get_property(ddata.cpu->of_node, "operating-points-v2", NULL)) {
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dev_err(ddata.cpu, "OPP-v2 not supported\n");
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goto skip_voltage_scaling;
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}
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ret = sti_cpufreq_fetch_syscon_registers();
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if (ret)
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goto skip_voltage_scaling;
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ret = sti_cpufreq_set_opp_info();
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if (!ret)
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goto register_cpufreq_dt;
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skip_voltage_scaling:
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dev_err(ddata.cpu, "Not doing voltage scaling\n");
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register_cpufreq_dt:
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platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
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return 0;
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}
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module_init(sti_cpufreq_init);
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static const struct of_device_id __maybe_unused sti_cpufreq_of_match[] = {
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{ .compatible = "st,stih407" },
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{ .compatible = "st,stih410" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sti_cpufreq_of_match);
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MODULE_DESCRIPTION("STMicroelectronics CPUFreq/OPP driver");
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MODULE_AUTHOR("Ajitpal Singh <ajitpal.singh@st.com>");
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MODULE_AUTHOR("Lee Jones <lee.jones@linaro.org>");
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MODULE_LICENSE("GPL v2");
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