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918e162e6a
* pm-cpufreq: cpufreq: Make cpufreq_generic_init() return void cpufreq: imx-cpufreq-dt: Add i.MX8MN support cpufreq: Add QoS requests for userspace constraints cpufreq: intel_pstate: Reuse refresh_frequency_limits() cpufreq: Register notifiers with the PM QoS framework PM / QoS: Add support for MIN/MAX frequency constraints PM / QOS: Pass request type to dev_pm_qos_read_value() PM / QOS: Rename __dev_pm_qos_read_value() and dev_pm_qos_raw_read_value() PM / QOS: Pass request type to dev_pm_qos_{add|remove}_notifier()
675 lines
18 KiB
C
675 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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* and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
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*
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* This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
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* that is iMac G5 and latest single CPU desktop.
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*/
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#undef DEBUG
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/cpufreq.h>
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#include <linux/init.h>
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/sections.h>
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#include <asm/cputable.h>
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#include <asm/time.h>
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#include <asm/smu.h>
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#include <asm/pmac_pfunc.h>
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#define DBG(fmt...) pr_debug(fmt)
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/* see 970FX user manual */
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#define SCOM_PCR 0x0aa001 /* PCR scom addr */
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#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
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#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
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#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
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#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
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#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
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#define PCR_SPEED_SHIFT 17
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#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
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#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
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#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
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#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
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#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
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#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
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#define SCOM_PSR 0x408001 /* PSR scom addr */
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/* warning: PSR is a 64 bits register */
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#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
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#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
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#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
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#define PSR_CUR_SPEED_SHIFT (56)
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/*
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* The G5 only supports two frequencies (Quarter speed is not supported)
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*/
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#define CPUFREQ_HIGH 0
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#define CPUFREQ_LOW 1
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static struct cpufreq_frequency_table g5_cpu_freqs[] = {
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{0, CPUFREQ_HIGH, 0},
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{0, CPUFREQ_LOW, 0},
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{0, 0, CPUFREQ_TABLE_END},
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};
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/* Power mode data is an array of the 32 bits PCR values to use for
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* the various frequencies, retrieved from the device-tree
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*/
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static int g5_pmode_cur;
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static void (*g5_switch_volt)(int speed_mode);
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static int (*g5_switch_freq)(int speed_mode);
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static int (*g5_query_freq)(void);
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static unsigned long transition_latency;
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#ifdef CONFIG_PMAC_SMU
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static const u32 *g5_pmode_data;
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static int g5_pmode_max;
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static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
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static int g5_fvt_count; /* number of op. points */
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static int g5_fvt_cur; /* current op. point */
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/*
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* SMU based voltage switching for Neo2 platforms
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*/
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static void g5_smu_switch_volt(int speed_mode)
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{
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struct smu_simple_cmd cmd;
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DECLARE_COMPLETION_ONSTACK(comp);
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smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
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&comp, 'V', 'S', 'L', 'E', 'W',
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0xff, g5_fvt_cur+1, speed_mode);
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wait_for_completion(&comp);
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}
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/*
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* Platform function based voltage/vdnap switching for Neo2
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*/
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static struct pmf_function *pfunc_set_vdnap0;
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static struct pmf_function *pfunc_vdnap0_complete;
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static void g5_vdnap_switch_volt(int speed_mode)
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{
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struct pmf_args args;
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u32 slew, done = 0;
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unsigned long timeout;
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slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
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args.count = 1;
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args.u[0].p = &slew;
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pmf_call_one(pfunc_set_vdnap0, &args);
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/* It's an irq GPIO so we should be able to just block here,
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* I'll do that later after I've properly tested the IRQ code for
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* platform functions
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*/
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timeout = jiffies + HZ/10;
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while(!time_after(jiffies, timeout)) {
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args.count = 1;
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args.u[0].p = &done;
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pmf_call_one(pfunc_vdnap0_complete, &args);
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if (done)
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break;
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usleep_range(1000, 1000);
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}
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if (done == 0)
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pr_warn("Timeout in clock slewing !\n");
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}
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/*
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* SCOM based frequency switching for 970FX rev3
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*/
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static int g5_scom_switch_freq(int speed_mode)
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{
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unsigned long flags;
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int to;
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/* If frequency is going up, first ramp up the voltage */
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if (speed_mode < g5_pmode_cur)
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g5_switch_volt(speed_mode);
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local_irq_save(flags);
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/* Clear PCR high */
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scom970_write(SCOM_PCR, 0);
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/* Clear PCR low */
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scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
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/* Set PCR low */
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scom970_write(SCOM_PCR, PCR_HILO_SELECT |
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g5_pmode_data[speed_mode]);
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/* Wait for completion */
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for (to = 0; to < 10; to++) {
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unsigned long psr = scom970_read(SCOM_PSR);
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if ((psr & PSR_CMD_RECEIVED) == 0 &&
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(((psr >> PSR_CUR_SPEED_SHIFT) ^
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(g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
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== 0)
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break;
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if (psr & PSR_CMD_COMPLETED)
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break;
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udelay(100);
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}
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local_irq_restore(flags);
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/* If frequency is going down, last ramp the voltage */
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if (speed_mode > g5_pmode_cur)
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g5_switch_volt(speed_mode);
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g5_pmode_cur = speed_mode;
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ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
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return 0;
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}
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static int g5_scom_query_freq(void)
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{
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unsigned long psr = scom970_read(SCOM_PSR);
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int i;
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for (i = 0; i <= g5_pmode_max; i++)
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if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
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(g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
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break;
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return i;
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}
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/*
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* Fake voltage switching for platforms with missing support
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*/
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static void g5_dummy_switch_volt(int speed_mode)
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{
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}
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#endif /* CONFIG_PMAC_SMU */
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/*
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* Platform function based voltage switching for PowerMac7,2 & 7,3
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*/
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static struct pmf_function *pfunc_cpu0_volt_high;
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static struct pmf_function *pfunc_cpu0_volt_low;
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static struct pmf_function *pfunc_cpu1_volt_high;
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static struct pmf_function *pfunc_cpu1_volt_low;
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static void g5_pfunc_switch_volt(int speed_mode)
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{
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if (speed_mode == CPUFREQ_HIGH) {
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if (pfunc_cpu0_volt_high)
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pmf_call_one(pfunc_cpu0_volt_high, NULL);
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if (pfunc_cpu1_volt_high)
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pmf_call_one(pfunc_cpu1_volt_high, NULL);
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} else {
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if (pfunc_cpu0_volt_low)
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pmf_call_one(pfunc_cpu0_volt_low, NULL);
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if (pfunc_cpu1_volt_low)
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pmf_call_one(pfunc_cpu1_volt_low, NULL);
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}
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usleep_range(10000, 10000); /* should be faster , to fix */
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}
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/*
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* Platform function based frequency switching for PowerMac7,2 & 7,3
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*/
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static struct pmf_function *pfunc_cpu_setfreq_high;
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static struct pmf_function *pfunc_cpu_setfreq_low;
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static struct pmf_function *pfunc_cpu_getfreq;
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static struct pmf_function *pfunc_slewing_done;
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static int g5_pfunc_switch_freq(int speed_mode)
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{
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struct pmf_args args;
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u32 done = 0;
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unsigned long timeout;
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int rc;
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DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
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/* If frequency is going up, first ramp up the voltage */
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if (speed_mode < g5_pmode_cur)
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g5_switch_volt(speed_mode);
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/* Do it */
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if (speed_mode == CPUFREQ_HIGH)
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rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
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else
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rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
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if (rc)
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pr_warn("pfunc switch error %d\n", rc);
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/* It's an irq GPIO so we should be able to just block here,
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* I'll do that later after I've properly tested the IRQ code for
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* platform functions
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*/
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timeout = jiffies + HZ/10;
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while(!time_after(jiffies, timeout)) {
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args.count = 1;
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args.u[0].p = &done;
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pmf_call_one(pfunc_slewing_done, &args);
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if (done)
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break;
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usleep_range(500, 500);
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}
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if (done == 0)
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pr_warn("Timeout in clock slewing !\n");
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/* If frequency is going down, last ramp the voltage */
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if (speed_mode > g5_pmode_cur)
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g5_switch_volt(speed_mode);
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g5_pmode_cur = speed_mode;
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ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
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return 0;
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}
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static int g5_pfunc_query_freq(void)
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{
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struct pmf_args args;
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u32 val = 0;
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args.count = 1;
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args.u[0].p = &val;
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pmf_call_one(pfunc_cpu_getfreq, &args);
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return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
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}
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/*
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* Common interface to the cpufreq core
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*/
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static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
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{
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return g5_switch_freq(index);
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}
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static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
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{
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return g5_cpu_freqs[g5_pmode_cur].frequency;
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}
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static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
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return 0;
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}
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static struct cpufreq_driver g5_cpufreq_driver = {
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.name = "powermac",
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.flags = CPUFREQ_CONST_LOOPS,
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.init = g5_cpufreq_cpu_init,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = g5_cpufreq_target,
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.get = g5_cpufreq_get_speed,
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.attr = cpufreq_generic_attr,
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};
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#ifdef CONFIG_PMAC_SMU
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static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
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{
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unsigned int psize, ssize;
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unsigned long max_freq;
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char *freq_method, *volt_method;
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const u32 *valp;
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u32 pvr_hi;
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int use_volts_vdnap = 0;
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int use_volts_smu = 0;
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int rc = -ENODEV;
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/* Check supported platforms */
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if (of_machine_is_compatible("PowerMac8,1") ||
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of_machine_is_compatible("PowerMac8,2") ||
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of_machine_is_compatible("PowerMac9,1") ||
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of_machine_is_compatible("PowerMac12,1"))
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use_volts_smu = 1;
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else if (of_machine_is_compatible("PowerMac11,2"))
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use_volts_vdnap = 1;
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else
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return -ENODEV;
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/* Check 970FX for now */
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valp = of_get_property(cpunode, "cpu-version", NULL);
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if (!valp) {
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DBG("No cpu-version property !\n");
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goto bail_noprops;
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}
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pvr_hi = (*valp) >> 16;
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if (pvr_hi != 0x3c && pvr_hi != 0x44) {
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pr_err("Unsupported CPU version\n");
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goto bail_noprops;
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}
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/* Look for the powertune data in the device-tree */
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g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
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if (!g5_pmode_data) {
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DBG("No power-mode-data !\n");
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goto bail_noprops;
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}
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g5_pmode_max = psize / sizeof(u32) - 1;
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if (use_volts_smu) {
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const struct smu_sdbp_header *shdr;
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/* Look for the FVT table */
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shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
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if (!shdr)
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goto bail_noprops;
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g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
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ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
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g5_fvt_count = ssize / sizeof(*g5_fvt_table);
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g5_fvt_cur = 0;
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/* Sanity checking */
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if (g5_fvt_count < 1 || g5_pmode_max < 1)
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goto bail_noprops;
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g5_switch_volt = g5_smu_switch_volt;
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volt_method = "SMU";
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} else if (use_volts_vdnap) {
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struct device_node *root;
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root = of_find_node_by_path("/");
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if (root == NULL) {
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pr_err("Can't find root of device tree\n");
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goto bail_noprops;
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}
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pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
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pfunc_vdnap0_complete =
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pmf_find_function(root, "slewing-done");
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of_node_put(root);
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if (pfunc_set_vdnap0 == NULL ||
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pfunc_vdnap0_complete == NULL) {
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pr_err("Can't find required platform function\n");
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goto bail_noprops;
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}
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g5_switch_volt = g5_vdnap_switch_volt;
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volt_method = "GPIO";
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} else {
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g5_switch_volt = g5_dummy_switch_volt;
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volt_method = "none";
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}
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/*
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* From what I see, clock-frequency is always the maximal frequency.
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* The current driver can not slew sysclk yet, so we really only deal
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* with powertune steps for now. We also only implement full freq and
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* half freq in this version. So far, I haven't yet seen a machine
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* supporting anything else.
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*/
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valp = of_get_property(cpunode, "clock-frequency", NULL);
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if (!valp)
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return -ENODEV;
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max_freq = (*valp)/1000;
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g5_cpu_freqs[0].frequency = max_freq;
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g5_cpu_freqs[1].frequency = max_freq/2;
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/* Set callbacks */
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transition_latency = 12000;
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g5_switch_freq = g5_scom_switch_freq;
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g5_query_freq = g5_scom_query_freq;
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freq_method = "SCOM";
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/* Force apply current frequency to make sure everything is in
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* sync (voltage is right for example). Firmware may leave us with
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* a strange setting ...
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*/
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g5_switch_volt(CPUFREQ_HIGH);
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msleep(10);
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g5_pmode_cur = -1;
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g5_switch_freq(g5_query_freq());
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pr_info("Registering G5 CPU frequency driver\n");
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pr_info("Frequency method: %s, Voltage method: %s\n",
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freq_method, volt_method);
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pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
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g5_cpu_freqs[1].frequency/1000,
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g5_cpu_freqs[0].frequency/1000,
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g5_cpu_freqs[g5_pmode_cur].frequency/1000);
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rc = cpufreq_register_driver(&g5_cpufreq_driver);
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/* We keep the CPU node on hold... hopefully, Apple G5 don't have
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* hotplug CPU with a dynamic device-tree ...
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*/
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return rc;
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bail_noprops:
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of_node_put(cpunode);
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return rc;
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}
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#endif /* CONFIG_PMAC_SMU */
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static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
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{
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|
struct device_node *cpuid = NULL, *hwclock = NULL;
|
|
const u8 *eeprom = NULL;
|
|
const u32 *valp;
|
|
u64 max_freq, min_freq, ih, il;
|
|
int has_volt = 1, rc = 0;
|
|
|
|
DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
|
|
" RackMac3,1...\n");
|
|
|
|
/* Lookup the cpuid eeprom node */
|
|
cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
|
|
if (cpuid != NULL)
|
|
eeprom = of_get_property(cpuid, "cpuid", NULL);
|
|
if (eeprom == NULL) {
|
|
pr_err("Can't find cpuid EEPROM !\n");
|
|
rc = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
/* Lookup the i2c hwclock */
|
|
for_each_node_by_name(hwclock, "i2c-hwclock") {
|
|
const char *loc = of_get_property(hwclock,
|
|
"hwctrl-location", NULL);
|
|
if (loc == NULL)
|
|
continue;
|
|
if (strcmp(loc, "CPU CLOCK"))
|
|
continue;
|
|
if (!of_get_property(hwclock, "platform-get-frequency", NULL))
|
|
continue;
|
|
break;
|
|
}
|
|
if (hwclock == NULL) {
|
|
pr_err("Can't find i2c clock chip !\n");
|
|
rc = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
DBG("cpufreq: i2c clock chip found: %pOF\n", hwclock);
|
|
|
|
/* Now get all the platform functions */
|
|
pfunc_cpu_getfreq =
|
|
pmf_find_function(hwclock, "get-frequency");
|
|
pfunc_cpu_setfreq_high =
|
|
pmf_find_function(hwclock, "set-frequency-high");
|
|
pfunc_cpu_setfreq_low =
|
|
pmf_find_function(hwclock, "set-frequency-low");
|
|
pfunc_slewing_done =
|
|
pmf_find_function(hwclock, "slewing-done");
|
|
pfunc_cpu0_volt_high =
|
|
pmf_find_function(hwclock, "set-voltage-high-0");
|
|
pfunc_cpu0_volt_low =
|
|
pmf_find_function(hwclock, "set-voltage-low-0");
|
|
pfunc_cpu1_volt_high =
|
|
pmf_find_function(hwclock, "set-voltage-high-1");
|
|
pfunc_cpu1_volt_low =
|
|
pmf_find_function(hwclock, "set-voltage-low-1");
|
|
|
|
/* Check we have minimum requirements */
|
|
if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
|
|
pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
|
|
pr_err("Can't find platform functions !\n");
|
|
rc = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
/* Check that we have complete sets */
|
|
if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
|
|
pmf_put_function(pfunc_cpu0_volt_high);
|
|
pmf_put_function(pfunc_cpu0_volt_low);
|
|
pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
|
|
has_volt = 0;
|
|
}
|
|
if (!has_volt ||
|
|
pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
|
|
pmf_put_function(pfunc_cpu1_volt_high);
|
|
pmf_put_function(pfunc_cpu1_volt_low);
|
|
pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
|
|
}
|
|
|
|
/* Note: The device tree also contains a "platform-set-values"
|
|
* function for which I haven't quite figured out the usage. It
|
|
* might have to be called on init and/or wakeup, I'm not too sure
|
|
* but things seem to work fine without it so far ...
|
|
*/
|
|
|
|
/* Get max frequency from device-tree */
|
|
valp = of_get_property(cpunode, "clock-frequency", NULL);
|
|
if (!valp) {
|
|
pr_err("Can't find CPU frequency !\n");
|
|
rc = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
max_freq = (*valp)/1000;
|
|
|
|
/* Now calculate reduced frequency by using the cpuid input freq
|
|
* ratio. This requires 64 bits math unless we are willing to lose
|
|
* some precision
|
|
*/
|
|
ih = *((u32 *)(eeprom + 0x10));
|
|
il = *((u32 *)(eeprom + 0x20));
|
|
|
|
/* Check for machines with no useful settings */
|
|
if (il == ih) {
|
|
pr_warn("No low frequency mode available on this model !\n");
|
|
rc = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
min_freq = 0;
|
|
if (ih != 0 && il != 0)
|
|
min_freq = (max_freq * il) / ih;
|
|
|
|
/* Sanity check */
|
|
if (min_freq >= max_freq || min_freq < 1000) {
|
|
pr_err("Can't calculate low frequency !\n");
|
|
rc = -ENXIO;
|
|
goto bail;
|
|
}
|
|
g5_cpu_freqs[0].frequency = max_freq;
|
|
g5_cpu_freqs[1].frequency = min_freq;
|
|
|
|
/* Based on a measurement on Xserve G5, rounded up. */
|
|
transition_latency = 10 * NSEC_PER_MSEC;
|
|
|
|
/* Set callbacks */
|
|
g5_switch_volt = g5_pfunc_switch_volt;
|
|
g5_switch_freq = g5_pfunc_switch_freq;
|
|
g5_query_freq = g5_pfunc_query_freq;
|
|
|
|
/* Force apply current frequency to make sure everything is in
|
|
* sync (voltage is right for example). Firmware may leave us with
|
|
* a strange setting ...
|
|
*/
|
|
g5_switch_volt(CPUFREQ_HIGH);
|
|
msleep(10);
|
|
g5_pmode_cur = -1;
|
|
g5_switch_freq(g5_query_freq());
|
|
|
|
pr_info("Registering G5 CPU frequency driver\n");
|
|
pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
|
|
has_volt ? "i2c/pfunc" : "none");
|
|
pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
|
|
g5_cpu_freqs[1].frequency/1000,
|
|
g5_cpu_freqs[0].frequency/1000,
|
|
g5_cpu_freqs[g5_pmode_cur].frequency/1000);
|
|
|
|
rc = cpufreq_register_driver(&g5_cpufreq_driver);
|
|
bail:
|
|
if (rc != 0) {
|
|
pmf_put_function(pfunc_cpu_getfreq);
|
|
pmf_put_function(pfunc_cpu_setfreq_high);
|
|
pmf_put_function(pfunc_cpu_setfreq_low);
|
|
pmf_put_function(pfunc_slewing_done);
|
|
pmf_put_function(pfunc_cpu0_volt_high);
|
|
pmf_put_function(pfunc_cpu0_volt_low);
|
|
pmf_put_function(pfunc_cpu1_volt_high);
|
|
pmf_put_function(pfunc_cpu1_volt_low);
|
|
}
|
|
of_node_put(hwclock);
|
|
of_node_put(cpuid);
|
|
of_node_put(cpunode);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int __init g5_cpufreq_init(void)
|
|
{
|
|
struct device_node *cpunode;
|
|
int rc = 0;
|
|
|
|
/* Get first CPU node */
|
|
cpunode = of_cpu_device_node_get(0);
|
|
if (cpunode == NULL) {
|
|
pr_err("Can't find any CPU node\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_machine_is_compatible("PowerMac7,2") ||
|
|
of_machine_is_compatible("PowerMac7,3") ||
|
|
of_machine_is_compatible("RackMac3,1"))
|
|
rc = g5_pm72_cpufreq_init(cpunode);
|
|
#ifdef CONFIG_PMAC_SMU
|
|
else
|
|
rc = g5_neo2_cpufreq_init(cpunode);
|
|
#endif /* CONFIG_PMAC_SMU */
|
|
|
|
return rc;
|
|
}
|
|
|
|
module_init(g5_cpufreq_init);
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|