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Kbuild test robot reports the following warning in lines 56 and 87 of drivers/mmc/host/meson-mx-sdhc-clkc.c: Using plain integer as NULL pointer Drop the integer value from the struct initialization to fix that warning. This will still ensure that the compiler will zero out the struct so it's in a well-defined state. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200517222907.1277787-2-martin.blumenstingl@googlemail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
159 lines
4.2 KiB
C
159 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic Meson SDHC clock controller
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*
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* Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include "meson-mx-sdhc.h"
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#define MESON_SDHC_NUM_BUILTIN_CLKS 6
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struct meson_mx_sdhc_clkc {
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struct clk_mux src_sel;
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struct clk_divider div;
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struct clk_gate mod_clk_en;
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struct clk_gate tx_clk_en;
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struct clk_gate rx_clk_en;
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struct clk_gate sd_clk_en;
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};
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static const struct clk_parent_data meson_mx_sdhc_src_sel_parents[4] = {
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{ .fw_name = "clkin0" },
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{ .fw_name = "clkin1" },
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{ .fw_name = "clkin2" },
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{ .fw_name = "clkin3" },
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};
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static const struct clk_div_table meson_mx_sdhc_div_table[] = {
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{ .div = 6, .val = 5, },
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{ .div = 8, .val = 7, },
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{ .div = 9, .val = 8, },
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{ .div = 10, .val = 9, },
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{ .div = 12, .val = 11, },
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{ .div = 16, .val = 15, },
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{ .div = 18, .val = 17, },
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{ .div = 34, .val = 33, },
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{ .div = 142, .val = 141, },
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{ .div = 850, .val = 849, },
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{ .div = 2126, .val = 2125, },
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{ .div = 4096, .val = 4095, },
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{ /* sentinel */ }
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};
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static int meson_mx_sdhc_clk_hw_register(struct device *dev,
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const char *name_suffix,
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const struct clk_parent_data *parents,
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unsigned int num_parents,
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const struct clk_ops *ops,
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struct clk_hw *hw)
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{
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struct clk_init_data init = { };
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char clk_name[32];
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snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dev),
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name_suffix);
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init.name = clk_name;
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init.ops = ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_data = parents;
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init.num_parents = num_parents;
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hw->init = &init;
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return devm_clk_hw_register(dev, hw);
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}
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static int meson_mx_sdhc_gate_clk_hw_register(struct device *dev,
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const char *name_suffix,
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struct clk_hw *parent,
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struct clk_hw *hw)
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{
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struct clk_parent_data parent_data = { .hw = parent };
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return meson_mx_sdhc_clk_hw_register(dev, name_suffix, &parent_data, 1,
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&clk_gate_ops, hw);
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}
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int meson_mx_sdhc_register_clkc(struct device *dev, void __iomem *base,
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struct clk_bulk_data *clk_bulk_data)
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{
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struct clk_parent_data div_parent = { };
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struct meson_mx_sdhc_clkc *clkc_data;
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int ret;
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clkc_data = devm_kzalloc(dev, sizeof(*clkc_data), GFP_KERNEL);
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if (!clkc_data)
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return -ENOMEM;
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clkc_data->src_sel.reg = base + MESON_SDHC_CLKC;
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clkc_data->src_sel.mask = 0x3;
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clkc_data->src_sel.shift = 16;
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ret = meson_mx_sdhc_clk_hw_register(dev, "src_sel",
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meson_mx_sdhc_src_sel_parents, 4,
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&clk_mux_ops,
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&clkc_data->src_sel.hw);
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if (ret)
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return ret;
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clkc_data->div.reg = base + MESON_SDHC_CLKC;
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clkc_data->div.shift = 0;
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clkc_data->div.width = 12;
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clkc_data->div.table = meson_mx_sdhc_div_table;
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div_parent.hw = &clkc_data->src_sel.hw;
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ret = meson_mx_sdhc_clk_hw_register(dev, "div", &div_parent, 1,
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&clk_divider_ops,
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&clkc_data->div.hw);
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if (ret)
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return ret;
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clkc_data->mod_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->mod_clk_en.bit_idx = 15;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "mod_clk_on",
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&clkc_data->div.hw,
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&clkc_data->mod_clk_en.hw);
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if (ret)
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return ret;
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clkc_data->tx_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->tx_clk_en.bit_idx = 14;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "tx_clk_on",
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&clkc_data->div.hw,
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&clkc_data->tx_clk_en.hw);
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if (ret)
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return ret;
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clkc_data->rx_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->rx_clk_en.bit_idx = 13;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "rx_clk_on",
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&clkc_data->div.hw,
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&clkc_data->rx_clk_en.hw);
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if (ret)
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return ret;
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clkc_data->sd_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->sd_clk_en.bit_idx = 12;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "sd_clk_on",
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&clkc_data->div.hw,
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&clkc_data->sd_clk_en.hw);
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if (ret)
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return ret;
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/*
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* TODO: Replace clk_hw.clk with devm_clk_hw_get_clk() once that is
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* available.
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*/
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clk_bulk_data[0].clk = clkc_data->mod_clk_en.hw.clk;
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clk_bulk_data[1].clk = clkc_data->sd_clk_en.hw.clk;
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clk_bulk_data[2].clk = clkc_data->tx_clk_en.hw.clk;
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clk_bulk_data[3].clk = clkc_data->rx_clk_en.hw.clk;
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return 0;
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}
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