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UART modules on Wondermedia SoCs are connected via a gated clock source, rather than directly to the 24Mhz reference clock. While uboot enables UART0 for debugging, other UART ports are unavailable until the clock is enabled. This patch checks that a valid clock is actually passed from devicetree, enables the clock in probe. This change removes the fallback when a clock was not specified as it doesn't apply any longer (and would only work if the UART clock was already enabled). DTSI files are updated for VT8500, WM8505 and WM8650. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
164 lines
3.2 KiB
Plaintext
164 lines
3.2 KiB
Plaintext
/*
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* wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* Licensed under GPLv2 or later
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "wm,wm8650";
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&intc0>;
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intc0: interrupt-controller@d8140000 {
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compatible = "via,vt8500-intc";
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interrupt-controller;
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reg = <0xd8140000 0x10000>;
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#interrupt-cells = <1>;
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};
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/* Secondary IC cascaded to intc0 */
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intc1: interrupt-controller@d8150000 {
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compatible = "via,vt8500-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xD8150000 0x10000>;
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interrupts = <56 57 58 59 60 61 62 63>;
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};
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gpio: gpio-controller@d8110000 {
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compatible = "wm,wm8650-gpio";
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gpio-controller;
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reg = <0xd8110000 0x10000>;
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#gpio-cells = <3>;
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};
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pmc@d8130000 {
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compatible = "via,vt8500-pmc";
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reg = <0xd8130000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ref25: ref25M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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ref24: ref24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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plla: plla {
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#clock-cells = <0>;
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compatible = "wm,wm8650-pll-clock";
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clocks = <&ref25>;
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reg = <0x200>;
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};
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pllb: pllb {
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#clock-cells = <0>;
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compatible = "wm,wm8650-pll-clock";
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clocks = <&ref25>;
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reg = <0x204>;
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};
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clkuart0: uart0 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x250>;
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enable-bit = <1>;
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};
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clkuart1: uart1 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&ref24>;
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enable-reg = <0x250>;
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enable-bit = <2>;
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};
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arm: arm {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&plla>;
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divisor-reg = <0x300>;
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};
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sdhc: sdhc {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x328>;
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divisor-mask = <0x3f>;
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enable-reg = <0x254>;
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enable-bit = <18>;
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};
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};
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};
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timer@d8130100 {
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compatible = "via,vt8500-timer";
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reg = <0xd8130100 0x28>;
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interrupts = <36>;
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};
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ehci@d8007900 {
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compatible = "via,vt8500-ehci";
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reg = <0xd8007900 0x200>;
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interrupts = <43>;
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};
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uhci@d8007b00 {
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compatible = "platform-uhci";
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reg = <0xd8007b00 0x200>;
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interrupts = <43>;
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};
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fb@d8050800 {
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compatible = "wm,wm8505-fb";
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reg = <0xd8050800 0x200>;
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display = <&display>;
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default-mode = <&mode0>;
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};
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ge_rops@d8050400 {
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compatible = "wm,prizm-ge-rops";
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reg = <0xd8050400 0x100>;
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};
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uart@d8200000 {
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compatible = "via,vt8500-uart";
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reg = <0xd8200000 0x1040>;
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interrupts = <32>;
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clocks = <&clkuart0>;
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};
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uart@d82b0000 {
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compatible = "via,vt8500-uart";
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reg = <0xd82b0000 0x1040>;
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interrupts = <33>;
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clocks = <&clkuart1>;
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};
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rtc@d8100000 {
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compatible = "via,vt8500-rtc";
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reg = <0xd8100000 0x10000>;
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interrupts = <48>;
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};
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};
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};
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