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940ab88962
For simple modules that contain a single platform_driver without any additional setup code then ends up being a block of duplicated boilerplate. This patch adds a new macro, module_platform_driver(), which replaces the module_init()/module_exit() registrations with template functions. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Reviewed-by: Magnus Damm <magnus.damm@gmail.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
546 lines
15 KiB
C
546 lines
15 KiB
C
/*
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* Xilinx SPI controller driver (master mode only)
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* Copyright (c) 2010 Secret Lab Technologies, Ltd.
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* Copyright (c) 2009 Intel Corporation
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* 2002-2007 (c) MontaVista Software, Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/spi/xilinx_spi.h>
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#include <linux/io.h>
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#define XILINX_SPI_NAME "xilinx_spi"
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/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
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* Product Specification", DS464
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*/
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#define XSPI_CR_OFFSET 0x60 /* Control Register */
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#define XSPI_CR_ENABLE 0x02
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#define XSPI_CR_MASTER_MODE 0x04
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#define XSPI_CR_CPOL 0x08
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#define XSPI_CR_CPHA 0x10
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#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
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#define XSPI_CR_TXFIFO_RESET 0x20
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#define XSPI_CR_RXFIFO_RESET 0x40
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#define XSPI_CR_MANUAL_SSELECT 0x80
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#define XSPI_CR_TRANS_INHIBIT 0x100
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#define XSPI_CR_LSB_FIRST 0x200
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#define XSPI_SR_OFFSET 0x64 /* Status Register */
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#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
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#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
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#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
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#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
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#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
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#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
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#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
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#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
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/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
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* IPIF registers are 32 bit
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*/
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#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
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#define XIPIF_V123B_GINTR_ENABLE 0x80000000
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#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
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#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
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#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
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#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
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* disabled */
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#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
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#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
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#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
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#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
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#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
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#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
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#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
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struct xilinx_spi {
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/* bitbang has to be first */
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struct spi_bitbang bitbang;
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struct completion done;
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struct resource mem; /* phys mem */
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void __iomem *regs; /* virt. address of the control registers */
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u32 irq;
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u8 *rx_ptr; /* pointer in the Tx buffer */
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const u8 *tx_ptr; /* pointer in the Rx buffer */
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int remaining_bytes; /* the number of bytes left to transfer */
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u8 bits_per_word;
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unsigned int (*read_fn) (void __iomem *);
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void (*write_fn) (u32, void __iomem *);
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void (*tx_fn) (struct xilinx_spi *);
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void (*rx_fn) (struct xilinx_spi *);
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};
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static void xspi_write32(u32 val, void __iomem *addr)
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{
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iowrite32(val, addr);
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}
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static unsigned int xspi_read32(void __iomem *addr)
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{
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return ioread32(addr);
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}
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static void xspi_write32_be(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static unsigned int xspi_read32_be(void __iomem *addr)
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{
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return ioread32be(addr);
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}
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static void xspi_tx8(struct xilinx_spi *xspi)
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{
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xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
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xspi->tx_ptr++;
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}
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static void xspi_tx16(struct xilinx_spi *xspi)
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{
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xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
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xspi->tx_ptr += 2;
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}
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static void xspi_tx32(struct xilinx_spi *xspi)
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{
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xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
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xspi->tx_ptr += 4;
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}
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static void xspi_rx8(struct xilinx_spi *xspi)
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{
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u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
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if (xspi->rx_ptr) {
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*xspi->rx_ptr = data & 0xff;
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xspi->rx_ptr++;
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}
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}
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static void xspi_rx16(struct xilinx_spi *xspi)
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{
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u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
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if (xspi->rx_ptr) {
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*(u16 *)(xspi->rx_ptr) = data & 0xffff;
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xspi->rx_ptr += 2;
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}
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}
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static void xspi_rx32(struct xilinx_spi *xspi)
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{
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u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
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if (xspi->rx_ptr) {
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*(u32 *)(xspi->rx_ptr) = data;
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xspi->rx_ptr += 4;
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}
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}
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static void xspi_init_hw(struct xilinx_spi *xspi)
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{
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void __iomem *regs_base = xspi->regs;
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/* Reset the SPI device */
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xspi->write_fn(XIPIF_V123B_RESET_MASK,
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regs_base + XIPIF_V123B_RESETR_OFFSET);
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/* Disable all the interrupts just in case */
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xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
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/* Enable the global IPIF interrupt */
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xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
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regs_base + XIPIF_V123B_DGIER_OFFSET);
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/* Deselect the slave on the SPI bus */
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xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
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/* Disable the transmitter, enable Manual Slave Select Assertion,
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* put SPI controller into master mode, and enable it */
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xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
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XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
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XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
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}
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static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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if (is_on == BITBANG_CS_INACTIVE) {
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/* Deselect the slave on the SPI bus */
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xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
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} else if (is_on == BITBANG_CS_ACTIVE) {
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/* Set the SPI clock phase and polarity */
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u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
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& ~XSPI_CR_MODE_MASK;
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if (spi->mode & SPI_CPHA)
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cr |= XSPI_CR_CPHA;
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if (spi->mode & SPI_CPOL)
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cr |= XSPI_CR_CPOL;
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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/* We do not check spi->max_speed_hz here as the SPI clock
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* frequency is not software programmable (the IP block design
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* parameter)
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*/
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/* Activate the chip select */
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xspi->write_fn(~(0x0001 << spi->chip_select),
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xspi->regs + XSPI_SSR_OFFSET);
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}
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}
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/* spi_bitbang requires custom setup_transfer() to be defined if there is a
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* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
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* supports 8 or 16 bits per word which cannot be changed in software.
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* SPI clock can't be changed in software either.
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* Check for correct bits per word. Chip select delay calculations could be
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* added here as soon as bitbang_work() can be made aware of the delay value.
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*/
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static int xilinx_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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u8 bits_per_word;
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bits_per_word = (t && t->bits_per_word)
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? t->bits_per_word : spi->bits_per_word;
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if (bits_per_word != xspi->bits_per_word) {
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dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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__func__, bits_per_word);
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return -EINVAL;
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}
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return 0;
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}
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static int xilinx_spi_setup(struct spi_device *spi)
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{
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/* always return 0, we can not check the number of bits.
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* There are cases when SPI setup is called before any driver is
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* there, in that case the SPI core defaults to 8 bits, which we
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* do not support in some cases. But if we return an error, the
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* SPI device would not be registered and no driver can get hold of it
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* When the driver is there, it will call SPI setup again with the
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* correct number of bits per transfer.
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* If a driver setups with the wrong bit number, it will fail when
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* it tries to do a transfer
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*/
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return 0;
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}
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static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
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{
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u8 sr;
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/* Fill the Tx FIFO with as many bytes as possible */
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
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if (xspi->tx_ptr)
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xspi->tx_fn(xspi);
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else
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xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
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xspi->remaining_bytes -= xspi->bits_per_word / 8;
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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}
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}
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static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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u32 ipif_ier;
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u16 cr;
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/* We get here with transmitter inhibited */
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xspi->tx_ptr = t->tx_buf;
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xspi->rx_ptr = t->rx_buf;
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xspi->remaining_bytes = t->len;
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INIT_COMPLETION(xspi->done);
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xilinx_spi_fill_tx_fifo(xspi);
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/* Enable the transmit empty interrupt, which we use to determine
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* progress on the transmission.
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*/
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ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
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xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
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xspi->regs + XIPIF_V123B_IIER_OFFSET);
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/* Start the transfer by not inhibiting the transmitter any longer */
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cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
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~XSPI_CR_TRANS_INHIBIT;
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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wait_for_completion(&xspi->done);
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/* Disable the transmit empty interrupt */
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xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
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return t->len - xspi->remaining_bytes;
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}
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/* This driver supports single master mode only. Hence Tx FIFO Empty
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* is the only interrupt we care about.
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* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
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* Fault are not to happen.
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*/
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static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
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{
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struct xilinx_spi *xspi = dev_id;
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u32 ipif_isr;
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/* Get the IPIF interrupts, and clear them immediately */
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ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
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xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
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if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
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u16 cr;
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u8 sr;
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/* A transmit has just completed. Process received data and
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* check for more data to transmit. Always inhibit the
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* transmitter while the Isr refills the transmit register/FIFO,
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* or make sure it is stopped if we're done.
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*/
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cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
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xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
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xspi->regs + XSPI_CR_OFFSET);
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/* Read out all the data from the Rx FIFO */
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
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xspi->rx_fn(xspi);
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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}
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/* See if there is more data to send */
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if (xspi->remaining_bytes > 0) {
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xilinx_spi_fill_tx_fifo(xspi);
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/* Start the transfer by not inhibiting the
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* transmitter any longer
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*/
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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} else {
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/* No more data to send.
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* Indicate the transfer is completed.
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*/
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complete(&xspi->done);
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}
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}
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return IRQ_HANDLED;
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}
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static const struct of_device_id xilinx_spi_of_match[] = {
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{ .compatible = "xlnx,xps-spi-2.00.a", },
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{ .compatible = "xlnx,xps-spi-2.00.b", },
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{}
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};
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MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
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struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
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u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word)
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{
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struct spi_master *master;
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struct xilinx_spi *xspi;
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int ret;
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master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
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if (!master)
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return NULL;
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/* the spi->mode bits understood by this driver: */
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master->mode_bits = SPI_CPOL | SPI_CPHA;
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xspi = spi_master_get_devdata(master);
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xspi->bitbang.master = spi_master_get(master);
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xspi->bitbang.chipselect = xilinx_spi_chipselect;
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xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
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xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
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xspi->bitbang.master->setup = xilinx_spi_setup;
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init_completion(&xspi->done);
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if (!request_mem_region(mem->start, resource_size(mem),
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XILINX_SPI_NAME))
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goto put_master;
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xspi->regs = ioremap(mem->start, resource_size(mem));
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if (xspi->regs == NULL) {
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dev_warn(dev, "ioremap failure\n");
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goto map_failed;
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}
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master->bus_num = bus_num;
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master->num_chipselect = num_cs;
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master->dev.of_node = dev->of_node;
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xspi->mem = *mem;
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xspi->irq = irq;
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if (little_endian) {
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xspi->read_fn = xspi_read32;
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xspi->write_fn = xspi_write32;
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} else {
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xspi->read_fn = xspi_read32_be;
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xspi->write_fn = xspi_write32_be;
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}
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xspi->bits_per_word = bits_per_word;
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if (xspi->bits_per_word == 8) {
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xspi->tx_fn = xspi_tx8;
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xspi->rx_fn = xspi_rx8;
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} else if (xspi->bits_per_word == 16) {
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xspi->tx_fn = xspi_tx16;
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xspi->rx_fn = xspi_rx16;
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} else if (xspi->bits_per_word == 32) {
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xspi->tx_fn = xspi_tx32;
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xspi->rx_fn = xspi_rx32;
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} else
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goto unmap_io;
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/* SPI controller initializations */
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xspi_init_hw(xspi);
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/* Register for SPI Interrupt */
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ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
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if (ret)
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goto unmap_io;
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ret = spi_bitbang_start(&xspi->bitbang);
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if (ret) {
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dev_err(dev, "spi_bitbang_start FAILED\n");
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goto free_irq;
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}
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dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
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(unsigned long long)mem->start, xspi->regs, xspi->irq);
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return master;
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free_irq:
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free_irq(xspi->irq, xspi);
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unmap_io:
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iounmap(xspi->regs);
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map_failed:
|
|
release_mem_region(mem->start, resource_size(mem));
|
|
put_master:
|
|
spi_master_put(master);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(xilinx_spi_init);
|
|
|
|
void xilinx_spi_deinit(struct spi_master *master)
|
|
{
|
|
struct xilinx_spi *xspi;
|
|
|
|
xspi = spi_master_get_devdata(master);
|
|
|
|
spi_bitbang_stop(&xspi->bitbang);
|
|
free_irq(xspi->irq, xspi);
|
|
iounmap(xspi->regs);
|
|
|
|
release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
|
|
spi_master_put(xspi->bitbang.master);
|
|
}
|
|
EXPORT_SYMBOL(xilinx_spi_deinit);
|
|
|
|
static int __devinit xilinx_spi_probe(struct platform_device *dev)
|
|
{
|
|
struct xspi_platform_data *pdata;
|
|
struct resource *r;
|
|
int irq, num_cs = 0, little_endian = 0, bits_per_word = 8;
|
|
struct spi_master *master;
|
|
u8 i;
|
|
|
|
pdata = dev->dev.platform_data;
|
|
if (pdata) {
|
|
num_cs = pdata->num_chipselect;
|
|
little_endian = pdata->little_endian;
|
|
bits_per_word = pdata->bits_per_word;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
if (dev->dev.of_node) {
|
|
const __be32 *prop;
|
|
int len;
|
|
|
|
/* number of slave select bits is required */
|
|
prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits",
|
|
&len);
|
|
if (prop && len >= sizeof(*prop))
|
|
num_cs = __be32_to_cpup(prop);
|
|
}
|
|
#endif
|
|
|
|
if (!num_cs) {
|
|
dev_err(&dev->dev, "Missing slave select configuration data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
|
|
r = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
|
if (!r)
|
|
return -ENODEV;
|
|
|
|
irq = platform_get_irq(dev, 0);
|
|
if (irq < 0)
|
|
return -ENXIO;
|
|
|
|
master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs,
|
|
little_endian, bits_per_word);
|
|
if (!master)
|
|
return -ENODEV;
|
|
|
|
if (pdata) {
|
|
for (i = 0; i < pdata->num_devices; i++)
|
|
spi_new_device(master, pdata->devices + i);
|
|
}
|
|
|
|
platform_set_drvdata(dev, master);
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit xilinx_spi_remove(struct platform_device *dev)
|
|
{
|
|
xilinx_spi_deinit(platform_get_drvdata(dev));
|
|
platform_set_drvdata(dev, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* work with hotplug and coldplug */
|
|
MODULE_ALIAS("platform:" XILINX_SPI_NAME);
|
|
|
|
static struct platform_driver xilinx_spi_driver = {
|
|
.probe = xilinx_spi_probe,
|
|
.remove = __devexit_p(xilinx_spi_remove),
|
|
.driver = {
|
|
.name = XILINX_SPI_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = xilinx_spi_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(xilinx_spi_driver);
|
|
|
|
MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
|
|
MODULE_DESCRIPTION("Xilinx SPI driver");
|
|
MODULE_LICENSE("GPL");
|