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ca632f5566
Sort the SPI makefile and enforce the naming convention spi_*.c for spi drivers. This change also rolls the contents of atmel_spi.h into the .c file since there is only one user of that particular include file. v2: - Use 'spi-' prefix instead of 'spi_' to match what seems to be be the predominant pattern for subsystem prefixes. - Clean up filenames in Kconfig and header comment blocks Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
638 lines
16 KiB
C
638 lines
16 KiB
C
/*
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* OMAP7xx SPI 100k controller driver
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* Author: Fabrice Crohas <fcrohas@gmail.com>
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* from original omap1_mcspi driver
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*
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* Copyright (C) 2005, 2006 Nokia Corporation
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* Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
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* Juha Yrj<72>l<EFBFBD> <juha.yrjola@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <plat/clock.h>
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#define OMAP1_SPI100K_MAX_FREQ 48000000
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#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
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#define SPI_SETUP1 0x00
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#define SPI_SETUP2 0x02
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#define SPI_CTRL 0x04
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#define SPI_STATUS 0x06
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#define SPI_TX_LSB 0x08
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#define SPI_TX_MSB 0x0a
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#define SPI_RX_LSB 0x0c
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#define SPI_RX_MSB 0x0e
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#define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
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#define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
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#define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
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#define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
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#define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
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#define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
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#define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
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#define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
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#define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
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#define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
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#define SPI_CTRL_SEN(x) ((x) << 7)
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#define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
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#define SPI_CTRL_WR (1UL << 1)
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#define SPI_CTRL_RD (1UL << 0)
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#define SPI_STATUS_WE (1UL << 1)
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#define SPI_STATUS_RD (1UL << 0)
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#define WRITE 0
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#define READ 1
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/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
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* cache operations; better heuristics consider wordsize and bitrate.
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*/
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#define DMA_MIN_BYTES 8
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#define SPI_RUNNING 0
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#define SPI_SHUTDOWN 1
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struct omap1_spi100k {
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struct work_struct work;
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/* lock protects queue and registers */
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spinlock_t lock;
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struct list_head msg_queue;
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struct spi_master *master;
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struct clk *ick;
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struct clk *fck;
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/* Virtual base address of the controller */
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void __iomem *base;
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/* State of the SPI */
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unsigned int state;
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};
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struct omap1_spi100k_cs {
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void __iomem *base;
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int word_len;
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};
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static struct workqueue_struct *omap1_spi100k_wq;
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#define MOD_REG_BIT(val, mask, set) do { \
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if (set) \
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val |= mask; \
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else \
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val &= ~mask; \
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} while (0)
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static void spi100k_enable_clock(struct spi_master *master)
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{
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unsigned int val;
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* enable SPI */
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val = readw(spi100k->base + SPI_SETUP1);
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val |= SPI_SETUP1_CLOCK_ENABLE;
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writew(val, spi100k->base + SPI_SETUP1);
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}
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static void spi100k_disable_clock(struct spi_master *master)
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{
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unsigned int val;
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* disable SPI */
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val = readw(spi100k->base + SPI_SETUP1);
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val &= ~SPI_SETUP1_CLOCK_ENABLE;
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writew(val, spi100k->base + SPI_SETUP1);
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}
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static void spi100k_write_data(struct spi_master *master, int len, int data)
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{
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* write 16-bit word, shifting 8-bit data if necessary */
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if (len <= 8) {
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data <<= 8;
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len = 16;
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}
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spi100k_enable_clock(master);
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writew( data , spi100k->base + SPI_TX_MSB);
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writew(SPI_CTRL_SEN(0) |
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SPI_CTRL_WORD_SIZE(len) |
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SPI_CTRL_WR,
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spi100k->base + SPI_CTRL);
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/* Wait for bit ack send change */
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while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE);
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udelay(1000);
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spi100k_disable_clock(master);
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}
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static int spi100k_read_data(struct spi_master *master, int len)
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{
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int dataH,dataL;
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* Always do at least 16 bits */
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if (len <= 8)
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len = 16;
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spi100k_enable_clock(master);
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writew(SPI_CTRL_SEN(0) |
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SPI_CTRL_WORD_SIZE(len) |
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SPI_CTRL_RD,
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spi100k->base + SPI_CTRL);
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while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD);
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udelay(1000);
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dataL = readw(spi100k->base + SPI_RX_LSB);
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dataH = readw(spi100k->base + SPI_RX_MSB);
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spi100k_disable_clock(master);
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return dataL;
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}
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static void spi100k_open(struct spi_master *master)
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{
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/* get control of SPI */
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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writew(SPI_SETUP1_INT_READ_ENABLE |
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SPI_SETUP1_INT_WRITE_ENABLE |
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SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
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/* configure clock and interrupts */
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writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
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SPI_SETUP2_NEGATIVE_LEVEL |
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SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
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}
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static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
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{
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if (enable)
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writew(0x05fc, spi100k->base + SPI_CTRL);
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else
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writew(0x05fd, spi100k->base + SPI_CTRL);
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}
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static unsigned
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omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct omap1_spi100k *spi100k;
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struct omap1_spi100k_cs *cs = spi->controller_state;
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unsigned int count, c;
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int word_len;
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spi100k = spi_master_get_devdata(spi->master);
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count = xfer->len;
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c = count;
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word_len = cs->word_len;
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if (word_len <= 8) {
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u8 *rx;
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const u8 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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c-=1;
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if (xfer->tx_buf != NULL)
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spi100k_write_data(spi->master, word_len, *tx++);
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if (xfer->rx_buf != NULL)
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*rx++ = spi100k_read_data(spi->master, word_len);
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} while(c);
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} else if (word_len <= 16) {
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u16 *rx;
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const u16 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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c-=2;
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if (xfer->tx_buf != NULL)
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spi100k_write_data(spi->master,word_len, *tx++);
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if (xfer->rx_buf != NULL)
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*rx++ = spi100k_read_data(spi->master,word_len);
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} while(c);
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} else if (word_len <= 32) {
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u32 *rx;
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const u32 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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c-=4;
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if (xfer->tx_buf != NULL)
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spi100k_write_data(spi->master,word_len, *tx);
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if (xfer->rx_buf != NULL)
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*rx = spi100k_read_data(spi->master,word_len);
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} while(c);
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}
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return count - c;
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}
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/* called only when no transfer is active to this device */
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static int omap1_spi100k_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
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struct omap1_spi100k_cs *cs = spi->controller_state;
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u8 word_len = spi->bits_per_word;
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if (t != NULL && t->bits_per_word)
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word_len = t->bits_per_word;
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if (!word_len)
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word_len = 8;
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if (spi->bits_per_word > 32)
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return -EINVAL;
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cs->word_len = word_len;
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/* SPI init before transfer */
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writew(0x3e , spi100k->base + SPI_SETUP1);
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writew(0x00 , spi100k->base + SPI_STATUS);
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writew(0x3e , spi100k->base + SPI_CTRL);
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return 0;
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
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static int omap1_spi100k_setup(struct spi_device *spi)
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{
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int ret;
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struct omap1_spi100k *spi100k;
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struct omap1_spi100k_cs *cs = spi->controller_state;
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if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
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dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
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spi->bits_per_word);
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return -EINVAL;
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}
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spi100k = spi_master_get_devdata(spi->master);
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if (!cs) {
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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cs->base = spi100k->base + spi->chip_select * 0x14;
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spi->controller_state = cs;
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}
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spi100k_open(spi->master);
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clk_enable(spi100k->ick);
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clk_enable(spi100k->fck);
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ret = omap1_spi100k_setup_transfer(spi, NULL);
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clk_disable(spi100k->ick);
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clk_disable(spi100k->fck);
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return ret;
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}
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static void omap1_spi100k_work(struct work_struct *work)
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{
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struct omap1_spi100k *spi100k;
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int status = 0;
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spi100k = container_of(work, struct omap1_spi100k, work);
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spin_lock_irq(&spi100k->lock);
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clk_enable(spi100k->ick);
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clk_enable(spi100k->fck);
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/* We only enable one channel at a time -- the one whose message is
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* at the head of the queue -- although this controller would gladly
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* arbitrate among multiple channels. This corresponds to "single
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* channel" master mode. As a side effect, we need to manage the
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* chipselect with the FORCE bit ... CS != channel enable.
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*/
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while (!list_empty(&spi100k->msg_queue)) {
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struct spi_message *m;
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struct spi_device *spi;
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struct spi_transfer *t = NULL;
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int cs_active = 0;
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struct omap1_spi100k_cs *cs;
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int par_override = 0;
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m = container_of(spi100k->msg_queue.next, struct spi_message,
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queue);
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list_del_init(&m->queue);
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spin_unlock_irq(&spi100k->lock);
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spi = m->spi;
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cs = spi->controller_state;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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status = -EINVAL;
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break;
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}
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if (par_override || t->speed_hz || t->bits_per_word) {
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par_override = 1;
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status = omap1_spi100k_setup_transfer(spi, t);
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if (status < 0)
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break;
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if (!t->speed_hz && !t->bits_per_word)
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par_override = 0;
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}
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if (!cs_active) {
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omap1_spi100k_force_cs(spi100k, 1);
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cs_active = 1;
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}
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if (t->len) {
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unsigned count;
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count = omap1_spi100k_txrx_pio(spi, t);
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m->actual_length += count;
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if (count != t->len) {
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status = -EIO;
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break;
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}
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}
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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/* ignore the "leave it on after last xfer" hint */
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if (t->cs_change) {
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omap1_spi100k_force_cs(spi100k, 0);
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cs_active = 0;
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}
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}
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/* Restore defaults if they were overriden */
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if (par_override) {
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par_override = 0;
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status = omap1_spi100k_setup_transfer(spi, NULL);
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}
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if (cs_active)
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omap1_spi100k_force_cs(spi100k, 0);
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m->status = status;
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m->complete(m->context);
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spin_lock_irq(&spi100k->lock);
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}
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clk_disable(spi100k->ick);
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clk_disable(spi100k->fck);
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spin_unlock_irq(&spi100k->lock);
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if (status < 0)
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printk(KERN_WARNING "spi transfer failed with %d\n", status);
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}
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static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m)
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{
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struct omap1_spi100k *spi100k;
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unsigned long flags;
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struct spi_transfer *t;
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m->actual_length = 0;
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m->status = -EINPROGRESS;
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spi100k = spi_master_get_devdata(spi->master);
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/* Don't accept new work if we're shutting down */
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if (spi100k->state == SPI_SHUTDOWN)
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return -ESHUTDOWN;
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/* reject invalid messages and transfers */
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if (list_empty(&m->transfers) || !m->complete)
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return -EINVAL;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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const void *tx_buf = t->tx_buf;
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void *rx_buf = t->rx_buf;
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unsigned len = t->len;
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if (t->speed_hz > OMAP1_SPI100K_MAX_FREQ
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|| (len && !(rx_buf || tx_buf))
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|| (t->bits_per_word &&
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( t->bits_per_word < 4
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|| t->bits_per_word > 32))) {
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dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
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t->speed_hz,
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len,
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tx_buf ? "tx" : "",
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rx_buf ? "rx" : "",
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t->bits_per_word);
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return -EINVAL;
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}
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if (t->speed_hz && t->speed_hz < OMAP1_SPI100K_MAX_FREQ/(1<<16)) {
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dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
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t->speed_hz,
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OMAP1_SPI100K_MAX_FREQ/(1<<16));
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return -EINVAL;
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}
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}
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spin_lock_irqsave(&spi100k->lock, flags);
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list_add_tail(&m->queue, &spi100k->msg_queue);
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queue_work(omap1_spi100k_wq, &spi100k->work);
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spin_unlock_irqrestore(&spi100k->lock, flags);
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return 0;
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}
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static int __init omap1_spi100k_reset(struct omap1_spi100k *spi100k)
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{
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return 0;
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}
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static int __devinit omap1_spi100k_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct omap1_spi100k *spi100k;
|
||
int status = 0;
|
||
|
||
if (!pdev->id)
|
||
return -EINVAL;
|
||
|
||
master = spi_alloc_master(&pdev->dev, sizeof *spi100k);
|
||
if (master == NULL) {
|
||
dev_dbg(&pdev->dev, "master allocation failed\n");
|
||
return -ENOMEM;
|
||
}
|
||
|
||
if (pdev->id != -1)
|
||
master->bus_num = pdev->id;
|
||
|
||
master->setup = omap1_spi100k_setup;
|
||
master->transfer = omap1_spi100k_transfer;
|
||
master->cleanup = NULL;
|
||
master->num_chipselect = 2;
|
||
master->mode_bits = MODEBITS;
|
||
|
||
dev_set_drvdata(&pdev->dev, master);
|
||
|
||
spi100k = spi_master_get_devdata(master);
|
||
spi100k->master = master;
|
||
|
||
/*
|
||
* The memory region base address is taken as the platform_data.
|
||
* You should allocate this with ioremap() before initializing
|
||
* the SPI.
|
||
*/
|
||
spi100k->base = (void __iomem *) pdev->dev.platform_data;
|
||
|
||
INIT_WORK(&spi100k->work, omap1_spi100k_work);
|
||
|
||
spin_lock_init(&spi100k->lock);
|
||
INIT_LIST_HEAD(&spi100k->msg_queue);
|
||
spi100k->ick = clk_get(&pdev->dev, "ick");
|
||
if (IS_ERR(spi100k->ick)) {
|
||
dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
|
||
status = PTR_ERR(spi100k->ick);
|
||
goto err1;
|
||
}
|
||
|
||
spi100k->fck = clk_get(&pdev->dev, "fck");
|
||
if (IS_ERR(spi100k->fck)) {
|
||
dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
|
||
status = PTR_ERR(spi100k->fck);
|
||
goto err2;
|
||
}
|
||
|
||
if (omap1_spi100k_reset(spi100k) < 0)
|
||
goto err3;
|
||
|
||
status = spi_register_master(master);
|
||
if (status < 0)
|
||
goto err3;
|
||
|
||
spi100k->state = SPI_RUNNING;
|
||
|
||
return status;
|
||
|
||
err3:
|
||
clk_put(spi100k->fck);
|
||
err2:
|
||
clk_put(spi100k->ick);
|
||
err1:
|
||
spi_master_put(master);
|
||
return status;
|
||
}
|
||
|
||
static int __exit omap1_spi100k_remove(struct platform_device *pdev)
|
||
{
|
||
struct spi_master *master;
|
||
struct omap1_spi100k *spi100k;
|
||
struct resource *r;
|
||
unsigned limit = 500;
|
||
unsigned long flags;
|
||
int status = 0;
|
||
|
||
master = dev_get_drvdata(&pdev->dev);
|
||
spi100k = spi_master_get_devdata(master);
|
||
|
||
spin_lock_irqsave(&spi100k->lock, flags);
|
||
|
||
spi100k->state = SPI_SHUTDOWN;
|
||
while (!list_empty(&spi100k->msg_queue) && limit--) {
|
||
spin_unlock_irqrestore(&spi100k->lock, flags);
|
||
msleep(10);
|
||
spin_lock_irqsave(&spi100k->lock, flags);
|
||
}
|
||
|
||
if (!list_empty(&spi100k->msg_queue))
|
||
status = -EBUSY;
|
||
|
||
spin_unlock_irqrestore(&spi100k->lock, flags);
|
||
|
||
if (status != 0)
|
||
return status;
|
||
|
||
clk_put(spi100k->fck);
|
||
clk_put(spi100k->ick);
|
||
|
||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
||
spi_unregister_master(master);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static struct platform_driver omap1_spi100k_driver = {
|
||
.driver = {
|
||
.name = "omap1_spi100k",
|
||
.owner = THIS_MODULE,
|
||
},
|
||
.remove = __exit_p(omap1_spi100k_remove),
|
||
};
|
||
|
||
|
||
static int __init omap1_spi100k_init(void)
|
||
{
|
||
omap1_spi100k_wq = create_singlethread_workqueue(
|
||
omap1_spi100k_driver.driver.name);
|
||
|
||
if (omap1_spi100k_wq == NULL)
|
||
return -1;
|
||
|
||
return platform_driver_probe(&omap1_spi100k_driver, omap1_spi100k_probe);
|
||
}
|
||
|
||
static void __exit omap1_spi100k_exit(void)
|
||
{
|
||
platform_driver_unregister(&omap1_spi100k_driver);
|
||
|
||
destroy_workqueue(omap1_spi100k_wq);
|
||
}
|
||
|
||
module_init(omap1_spi100k_init);
|
||
module_exit(omap1_spi100k_exit);
|
||
|
||
MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
|
||
MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
|
||
MODULE_LICENSE("GPL");
|
||
|