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137c9e08e5
Add support for watchdog and reset generator unit of the MediaTek MT7988 SoC. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
523 lines
13 KiB
C
523 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Mediatek Watchdog Driver
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*
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* Copyright (C) 2014 Matthias Brugger
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*
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* Matthias Brugger <matthias.bgg@gmail.com>
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*
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* Based on sunxi_wdt.c
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*/
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#include <dt-bindings/reset/mt2712-resets.h>
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#include <dt-bindings/reset/mediatek,mt6795-resets.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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#include <dt-bindings/reset/mt8183-resets.h>
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#include <dt-bindings/reset/mt8186-resets.h>
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#include <dt-bindings/reset/mt8188-resets.h>
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#include <dt-bindings/reset/mt8192-resets.h>
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#include <dt-bindings/reset/mt8195-resets.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#include <linux/interrupt.h>
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#define WDT_MAX_TIMEOUT 31
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#define WDT_MIN_TIMEOUT 2
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#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
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#define WDT_LENGTH 0x04
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#define WDT_LENGTH_KEY 0x8
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#define WDT_RST 0x08
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#define WDT_RST_RELOAD 0x1971
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#define WDT_MODE 0x00
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#define WDT_MODE_EN (1 << 0)
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#define WDT_MODE_EXT_POL_LOW (0 << 1)
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#define WDT_MODE_EXT_POL_HIGH (1 << 1)
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#define WDT_MODE_EXRST_EN (1 << 2)
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#define WDT_MODE_IRQ_EN (1 << 3)
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#define WDT_MODE_AUTO_START (1 << 4)
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#define WDT_MODE_DUAL_EN (1 << 6)
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#define WDT_MODE_CNT_SEL (1 << 8)
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#define WDT_MODE_KEY 0x22000000
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#define WDT_SWRST 0x14
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#define WDT_SWRST_KEY 0x1209
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#define WDT_SWSYSRST 0x18U
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#define WDT_SWSYS_RST_KEY 0x88000000
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#define WDT_SWSYSRST_EN 0xfc
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#define DRV_NAME "mtk-wdt"
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#define DRV_VERSION "1.0"
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#define MT7988_TOPRGU_SW_RST_NUM 24
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static unsigned int timeout;
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struct mtk_wdt_dev {
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struct watchdog_device wdt_dev;
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void __iomem *wdt_base;
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spinlock_t lock; /* protects WDT_SWSYSRST reg */
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struct reset_controller_dev rcdev;
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bool disable_wdt_extrst;
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bool reset_by_toprgu;
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bool has_swsysrst_en;
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};
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struct mtk_wdt_data {
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int toprgu_sw_rst_num;
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bool has_swsysrst_en;
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};
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static const struct mtk_wdt_data mt2712_data = {
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.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt6795_data = {
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.toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt7986_data = {
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.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt7988_data = {
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.toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
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.has_swsysrst_en = true,
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};
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static const struct mtk_wdt_data mt8183_data = {
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.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt8186_data = {
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.toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt8188_data = {
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.toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt8192_data = {
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.toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
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};
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static const struct mtk_wdt_data mt8195_data = {
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.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
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};
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/**
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* toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
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* @data: Pointer to instance of driver data.
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* @id: Bit number identifying the reset to be enabled or disabled.
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* @enable: If true, enable software control for that bit, disable otherwise.
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*
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* Context: The caller must hold lock of struct mtk_wdt_dev.
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*/
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static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
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unsigned long id, bool enable)
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{
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u32 tmp;
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tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
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if (enable)
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tmp |= BIT(id);
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else
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tmp &= ~BIT(id);
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writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
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}
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static int toprgu_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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unsigned int tmp;
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unsigned long flags;
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struct mtk_wdt_dev *data =
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container_of(rcdev, struct mtk_wdt_dev, rcdev);
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spin_lock_irqsave(&data->lock, flags);
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if (assert && data->has_swsysrst_en)
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toprgu_reset_sw_en_unlocked(data, id, true);
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tmp = readl(data->wdt_base + WDT_SWSYSRST);
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if (assert)
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tmp |= BIT(id);
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else
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tmp &= ~BIT(id);
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tmp |= WDT_SWSYS_RST_KEY;
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writel(tmp, data->wdt_base + WDT_SWSYSRST);
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if (!assert && data->has_swsysrst_en)
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toprgu_reset_sw_en_unlocked(data, id, false);
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return toprgu_reset_update(rcdev, id, true);
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}
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static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return toprgu_reset_update(rcdev, id, false);
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}
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static int toprgu_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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ret = toprgu_reset_assert(rcdev, id);
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if (ret)
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return ret;
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return toprgu_reset_deassert(rcdev, id);
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}
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static const struct reset_control_ops toprgu_reset_ops = {
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.assert = toprgu_reset_assert,
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.deassert = toprgu_reset_deassert,
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.reset = toprgu_reset,
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};
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static int toprgu_register_reset_controller(struct platform_device *pdev,
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int rst_num)
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{
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int ret;
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struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
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spin_lock_init(&mtk_wdt->lock);
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mtk_wdt->rcdev.owner = THIS_MODULE;
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mtk_wdt->rcdev.nr_resets = rst_num;
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mtk_wdt->rcdev.ops = &toprgu_reset_ops;
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mtk_wdt->rcdev.of_node = pdev->dev.of_node;
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ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
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if (ret != 0)
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dev_err(&pdev->dev,
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"couldn't register wdt reset controller: %d\n", ret);
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return ret;
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}
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static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
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unsigned long action, void *data)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base;
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wdt_base = mtk_wdt->wdt_base;
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while (1) {
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writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
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mdelay(5);
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}
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return 0;
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}
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static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
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return 0;
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}
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static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int timeout)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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u32 reg;
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wdt_dev->timeout = timeout;
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/*
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* In dual mode, irq will be triggered at timeout / 2
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* the real timeout occurs at timeout
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*/
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if (wdt_dev->pretimeout)
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wdt_dev->pretimeout = timeout / 2;
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/*
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* One bit is the value of 512 ticks
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* The clock has 32 KHz
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*/
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reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
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| WDT_LENGTH_KEY;
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iowrite32(reg, wdt_base + WDT_LENGTH);
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mtk_wdt_ping(wdt_dev);
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return 0;
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}
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static void mtk_wdt_init(struct watchdog_device *wdt_dev)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base;
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wdt_base = mtk_wdt->wdt_base;
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if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
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set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
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mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
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}
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}
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static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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u32 reg;
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reg = readl(wdt_base + WDT_MODE);
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reg &= ~WDT_MODE_EN;
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reg |= WDT_MODE_KEY;
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iowrite32(reg, wdt_base + WDT_MODE);
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return 0;
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}
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static int mtk_wdt_start(struct watchdog_device *wdt_dev)
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{
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u32 reg;
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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int ret;
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ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
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if (ret < 0)
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return ret;
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reg = ioread32(wdt_base + WDT_MODE);
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if (wdt_dev->pretimeout)
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reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
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else
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reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
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if (mtk_wdt->disable_wdt_extrst)
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reg &= ~WDT_MODE_EXRST_EN;
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if (mtk_wdt->reset_by_toprgu)
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reg |= WDT_MODE_CNT_SEL;
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reg |= (WDT_MODE_EN | WDT_MODE_KEY);
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iowrite32(reg, wdt_base + WDT_MODE);
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return 0;
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}
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static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
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void __iomem *wdt_base = mtk_wdt->wdt_base;
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u32 reg = ioread32(wdt_base + WDT_MODE);
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if (timeout && !wdd->pretimeout) {
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wdd->pretimeout = wdd->timeout / 2;
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reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
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} else if (!timeout && wdd->pretimeout) {
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wdd->pretimeout = 0;
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reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
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} else {
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return 0;
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}
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reg |= WDT_MODE_KEY;
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iowrite32(reg, wdt_base + WDT_MODE);
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return mtk_wdt_set_timeout(wdd, wdd->timeout);
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}
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static irqreturn_t mtk_wdt_isr(int irq, void *arg)
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{
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struct watchdog_device *wdd = arg;
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watchdog_notify_pretimeout(wdd);
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return IRQ_HANDLED;
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}
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static const struct watchdog_info mtk_wdt_info = {
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.identity = DRV_NAME,
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.options = WDIOF_SETTIMEOUT |
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WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_info mtk_wdt_pt_info = {
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.identity = DRV_NAME,
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.options = WDIOF_SETTIMEOUT |
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WDIOF_PRETIMEOUT |
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WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops mtk_wdt_ops = {
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.owner = THIS_MODULE,
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.start = mtk_wdt_start,
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.stop = mtk_wdt_stop,
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.ping = mtk_wdt_ping,
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.set_timeout = mtk_wdt_set_timeout,
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.set_pretimeout = mtk_wdt_set_pretimeout,
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.restart = mtk_wdt_restart,
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};
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static int mtk_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_wdt_dev *mtk_wdt;
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const struct mtk_wdt_data *wdt_data;
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int err, irq;
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mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
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if (!mtk_wdt)
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return -ENOMEM;
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platform_set_drvdata(pdev, mtk_wdt);
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mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mtk_wdt->wdt_base))
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return PTR_ERR(mtk_wdt->wdt_base);
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irq = platform_get_irq_optional(pdev, 0);
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if (irq > 0) {
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err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
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&mtk_wdt->wdt_dev);
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if (err)
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return err;
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mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
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mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
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} else {
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if (irq == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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mtk_wdt->wdt_dev.info = &mtk_wdt_info;
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}
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mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
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mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
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mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
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mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
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mtk_wdt->wdt_dev.parent = dev;
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watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
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watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
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watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
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watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
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mtk_wdt_init(&mtk_wdt->wdt_dev);
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watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
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err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
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if (unlikely(err))
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return err;
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dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
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mtk_wdt->wdt_dev.timeout, nowayout);
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wdt_data = of_device_get_match_data(dev);
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if (wdt_data) {
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err = toprgu_register_reset_controller(pdev,
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wdt_data->toprgu_sw_rst_num);
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if (err)
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return err;
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mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
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}
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mtk_wdt->disable_wdt_extrst =
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of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
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mtk_wdt->reset_by_toprgu =
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of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");
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return 0;
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}
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static int mtk_wdt_suspend(struct device *dev)
|
|
{
|
|
struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
|
|
|
|
if (watchdog_active(&mtk_wdt->wdt_dev))
|
|
mtk_wdt_stop(&mtk_wdt->wdt_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_wdt_resume(struct device *dev)
|
|
{
|
|
struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
|
|
|
|
if (watchdog_active(&mtk_wdt->wdt_dev)) {
|
|
mtk_wdt_start(&mtk_wdt->wdt_dev);
|
|
mtk_wdt_ping(&mtk_wdt->wdt_dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mtk_wdt_dt_ids[] = {
|
|
{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
|
|
{ .compatible = "mediatek,mt6589-wdt" },
|
|
{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
|
|
{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
|
|
{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
|
|
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
|
|
{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
|
|
{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
|
|
{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
|
|
{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
|
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
|
|
mtk_wdt_suspend, mtk_wdt_resume);
|
|
|
|
static struct platform_driver mtk_wdt_driver = {
|
|
.probe = mtk_wdt_probe,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.pm = pm_sleep_ptr(&mtk_wdt_pm_ops),
|
|
.of_match_table = mtk_wdt_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mtk_wdt_driver);
|
|
|
|
module_param(timeout, uint, 0);
|
|
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
|
|
|
|
module_param(nowayout, bool, 0);
|
|
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
|
|
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
|
|
MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
|
|
MODULE_VERSION(DRV_VERSION);
|