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Introduce a rseq-arm-bits.h template header which is internally included to generate the static inline functions covering: - relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-13-mathieu.desnoyers@efficios.com
177 lines
6.0 KiB
C
177 lines
6.0 KiB
C
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* rseq-arm.h
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*
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* (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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*/
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/*
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* - ARM little endian
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*
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* RSEQ_SIG uses the udf A32 instruction with an uncommon immediate operand
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* value 0x5de3. This traps if user-space reaches this instruction by mistake,
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* and the uncommon operand ensures the kernel does not move the instruction
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* pointer to attacker-controlled code on rseq abort.
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*
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* The instruction pattern in the A32 instruction set is:
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*
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* e7f5def3 udf #24035 ; 0x5de3
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*
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* This translates to the following instruction pattern in the T16 instruction
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* set:
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*
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* little endian:
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* def3 udf #243 ; 0xf3
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* e7f5 b.n <7f5>
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*
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* - ARMv6+ big endian (BE8):
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*
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* ARMv6+ -mbig-endian generates mixed endianness code vs data: little-endian
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* code and big-endian data. The data value of the signature needs to have its
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* byte order reversed to generate the trap instruction:
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*
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* Data: 0xf3def5e7
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*
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* Translates to this A32 instruction pattern:
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*
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* e7f5def3 udf #24035 ; 0x5de3
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*
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* Translates to this T16 instruction pattern:
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*
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* def3 udf #243 ; 0xf3
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* e7f5 b.n <7f5>
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*
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* - Prior to ARMv6 big endian (BE32):
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*
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* Prior to ARMv6, -mbig-endian generates big-endian code and data
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* (which match), so the endianness of the data representation of the
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* signature should not be reversed. However, the choice between BE32
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* and BE8 is done by the linker, so we cannot know whether code and
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* data endianness will be mixed before the linker is invoked. So rather
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* than try to play tricks with the linker, the rseq signature is simply
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* data (not a trap instruction) prior to ARMv6 on big endian. This is
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* why the signature is expressed as data (.word) rather than as
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* instruction (.inst) in assembler.
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*/
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#ifdef __ARMEB__
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#define RSEQ_SIG 0xf3def5e7 /* udf #24035 ; 0x5de3 (ARMv6+) */
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#else
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#define RSEQ_SIG 0xe7f5def3 /* udf #24035 ; 0x5de3 */
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#endif
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#define rseq_smp_mb() __asm__ __volatile__ ("dmb" ::: "memory", "cc")
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#define rseq_smp_rmb() __asm__ __volatile__ ("dmb" ::: "memory", "cc")
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#define rseq_smp_wmb() __asm__ __volatile__ ("dmb" ::: "memory", "cc")
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#define rseq_smp_load_acquire(p) \
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__extension__ ({ \
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__typeof(*p) ____p1 = RSEQ_READ_ONCE(*p); \
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rseq_smp_mb(); \
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____p1; \
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})
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#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
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#define rseq_smp_store_release(p, v) \
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do { \
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rseq_smp_mb(); \
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RSEQ_WRITE_ONCE(*p, v); \
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} while (0)
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#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
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post_commit_offset, abort_ip) \
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".pushsection __rseq_cs, \"aw\"\n\t" \
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".balign 32\n\t" \
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__rseq_str(label) ":\n\t" \
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".word " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
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".word " __rseq_str(start_ip) ", 0x0, " __rseq_str(post_commit_offset) ", 0x0, " __rseq_str(abort_ip) ", 0x0\n\t" \
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".popsection\n\t" \
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".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \
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".word " __rseq_str(label) "b, 0x0\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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/*
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* Exit points of a rseq critical section consist of all instructions outside
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* of the critical section where a critical section can either branch to or
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* reach through the normal course of its execution. The abort IP and the
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* post-commit IP are already part of the __rseq_cs section and should not be
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* explicitly defined as additional exit points. Knowing all exit points is
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* useful to assist debuggers stepping over the critical section.
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*/
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#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
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".pushsection __rseq_exit_point_array, \"aw\"\n\t" \
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".word " __rseq_str(start_ip) ", 0x0, " __rseq_str(exit_ip) ", 0x0\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
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RSEQ_INJECT_ASM(1) \
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"adr r0, " __rseq_str(cs_label) "\n\t" \
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"str r0, %[" __rseq_str(rseq_cs) "]\n\t" \
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__rseq_str(label) ":\n\t"
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#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
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RSEQ_INJECT_ASM(2) \
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"ldr r0, %[" __rseq_str(current_cpu_id) "]\n\t" \
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"cmp %[" __rseq_str(cpu_id) "], r0\n\t" \
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"bne " __rseq_str(label) "\n\t"
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#define __RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, \
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abort_label, version, flags, \
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start_ip, post_commit_offset, abort_ip) \
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".balign 32\n\t" \
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__rseq_str(table_label) ":\n\t" \
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".word " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
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".word " __rseq_str(start_ip) ", 0x0, " __rseq_str(post_commit_offset) ", 0x0, " __rseq_str(abort_ip) ", 0x0\n\t" \
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".word " __rseq_str(RSEQ_SIG) "\n\t" \
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__rseq_str(label) ":\n\t" \
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teardown \
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"b %l[" __rseq_str(abort_label) "]\n\t"
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#define RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, abort_label, \
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start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, \
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abort_label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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#define RSEQ_ASM_DEFINE_CMPFAIL(label, teardown, cmpfail_label) \
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__rseq_str(label) ":\n\t" \
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teardown \
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"b %l[" __rseq_str(cmpfail_label) "]\n\t"
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/* Per-cpu-id indexing. */
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#define RSEQ_TEMPLATE_CPU_ID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-arm-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-arm-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_CPU_ID
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/* Per-mm-cid indexing. */
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#define RSEQ_TEMPLATE_MM_CID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-arm-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-arm-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_MM_CID
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/* APIs which are not based on cpu ids. */
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#define RSEQ_TEMPLATE_CPU_ID_NONE
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-arm-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#undef RSEQ_TEMPLATE_CPU_ID_NONE
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