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94fb175c04
1/ regression fix for Xen as it now trips over a broken assumption about the dma address size on 32-bit builds 2/ new quirk for netdma to ignore dma channels that cannot meet netdma alignment requirements 3/ fixes for two long standing issues in ioatdma (ring size overflow) and iop-adma (potential stack corruption) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPhIfhAAoJEB7SkWpmfYgCguIQAL4qF+RC9/JggSHIjfOrYiPd yboV80GqqQHHBwy8hfZVUrIEPMebvD/xUIk6iUQNXR+6EA8Ln0jukvQMpWNnI+Cc TXgA5Ok70an4PD1MqnCsWyCJjsyPyhprbRHurxBcesf+y96POJxhING0rcKvft50 mvYnbtrkYe9M9x3b8TBGc0JaTVeL29Ck3FtkTz4uUktbkhRNfCcfEd28NRQpf8MB vkjbjRGBQmGsnKxYCaEhlF1GPJyTlYjg4BBWtseJgb2R9s7tvJrkotFea/NmSfjq XCuVKjpiFp3YyJuxJERWdwqRWvyAZFfcYyZX440nG0b7GBgSn+T7A9XhUs8vMboi tLwoDfBbJDlKMaFpHex7Z6RtZZmVl3gWDNZTqpG44n4pabd4RPip04f0k7Wfs+cp tzU9hGAOvgsZ8w4/JgxH8YJOZbIGzbDGOA1IhWcbxIbmFTblMiFnV3TC7qfhoRbR 8qtScIE7bUck2MYVlMMn9utd9tvKFa6HNgo41+f78/4+U7zQ/VrsbA/DWQct40R5 5k+EEvyYFUzIXn79E0GVN5h4NHH5gfAs3MZ7jIgwgHedBp4Ki68XYKNu+pIV3YwG CFTPn1mVOXnCdt+fsjG5tL9Jecx1Mij6w3nWU93ZU6cHmC77YmU+DLxPIGuyR1a2 EmpObwfq5peXzkgQpEsB =F3IR -----END PGP SIGNATURE----- Merge tag 'dmaengine-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/dmaengine Pull dmaengine fixes from Dan Williams: 1/ regression fix for Xen as it now trips over a broken assumption about the dma address size on 32-bit builds 2/ new quirk for netdma to ignore dma channels that cannot meet netdma alignment requirements 3/ fixes for two long standing issues in ioatdma (ring size overflow) and iop-adma (potential stack corruption) * tag 'dmaengine-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/dmaengine: netdma: adding alignment check for NETDMA ops ioatdma: DMA copy alignment needed to address IOAT DMA silicon errata ioat: ring size variables need to be 32bit to avoid overflow iop-adma: Corrected array overflow in RAID6 Xscale(R) test. ioat: fix size of 'completion' for Xen
1072 lines
28 KiB
C
1072 lines
28 KiB
C
/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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/*
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* This code implements the DMA subsystem. It provides a HW-neutral interface
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* for other kernel code to use asynchronous memory copy capabilities,
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* if present, and allows different HW DMA drivers to register as providing
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* this capability.
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*
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* Due to the fact we are accelerating what is already a relatively fast
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* operation, the code goes to great lengths to avoid additional overhead,
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* such as locking.
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*
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* LOCKING:
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*
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* The subsystem keeps a global list of dma_device structs it is protected by a
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* mutex, dma_list_mutex.
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*
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* A subsystem can get access to a channel by calling dmaengine_get() followed
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* by dma_find_channel(), or if it has need for an exclusive channel it can call
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* dma_request_channel(). Once a channel is allocated a reference is taken
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* against its corresponding driver to disable removal.
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*
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* Each device has a channels list, which runs unlocked but is never modified
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* once the device is registered, it's just setup by the driver.
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*
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* See Documentation/dmaengine.txt for more details
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*/
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/hardirq.h>
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#include <linux/spinlock.h>
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#include <linux/percpu.h>
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#include <linux/rcupdate.h>
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#include <linux/mutex.h>
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#include <linux/jiffies.h>
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#include <linux/rculist.h>
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#include <linux/idr.h>
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#include <linux/slab.h>
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static DEFINE_MUTEX(dma_list_mutex);
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static DEFINE_IDR(dma_idr);
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static LIST_HEAD(dma_device_list);
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static long dmaengine_ref_count;
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/* --- sysfs implementation --- */
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/**
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* dev_to_dma_chan - convert a device pointer to the its sysfs container object
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* @dev - device node
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*
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* Must be called under dma_list_mutex
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*/
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static struct dma_chan *dev_to_dma_chan(struct device *dev)
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{
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struct dma_chan_dev *chan_dev;
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chan_dev = container_of(dev, typeof(*chan_dev), device);
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return chan_dev->chan;
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}
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static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
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{
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struct dma_chan *chan;
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unsigned long count = 0;
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int i;
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int err;
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mutex_lock(&dma_list_mutex);
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chan = dev_to_dma_chan(dev);
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if (chan) {
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for_each_possible_cpu(i)
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count += per_cpu_ptr(chan->local, i)->memcpy_count;
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err = sprintf(buf, "%lu\n", count);
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} else
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err = -ENODEV;
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mutex_unlock(&dma_list_mutex);
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return err;
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}
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static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct dma_chan *chan;
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unsigned long count = 0;
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int i;
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int err;
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mutex_lock(&dma_list_mutex);
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chan = dev_to_dma_chan(dev);
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if (chan) {
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for_each_possible_cpu(i)
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count += per_cpu_ptr(chan->local, i)->bytes_transferred;
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err = sprintf(buf, "%lu\n", count);
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} else
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err = -ENODEV;
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mutex_unlock(&dma_list_mutex);
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return err;
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}
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static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
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{
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struct dma_chan *chan;
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int err;
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mutex_lock(&dma_list_mutex);
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chan = dev_to_dma_chan(dev);
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if (chan)
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err = sprintf(buf, "%d\n", chan->client_count);
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else
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err = -ENODEV;
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mutex_unlock(&dma_list_mutex);
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return err;
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}
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static struct device_attribute dma_attrs[] = {
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__ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
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__ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
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__ATTR(in_use, S_IRUGO, show_in_use, NULL),
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__ATTR_NULL
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};
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static void chan_dev_release(struct device *dev)
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{
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struct dma_chan_dev *chan_dev;
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chan_dev = container_of(dev, typeof(*chan_dev), device);
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if (atomic_dec_and_test(chan_dev->idr_ref)) {
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mutex_lock(&dma_list_mutex);
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idr_remove(&dma_idr, chan_dev->dev_id);
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mutex_unlock(&dma_list_mutex);
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kfree(chan_dev->idr_ref);
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}
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kfree(chan_dev);
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}
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static struct class dma_devclass = {
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.name = "dma",
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.dev_attrs = dma_attrs,
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.dev_release = chan_dev_release,
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};
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/* --- client and device registration --- */
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#define dma_device_satisfies_mask(device, mask) \
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__dma_device_satisfies_mask((device), &(mask))
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static int
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__dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
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{
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dma_cap_mask_t has;
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bitmap_and(has.bits, want->bits, device->cap_mask.bits,
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DMA_TX_TYPE_END);
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return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
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}
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static struct module *dma_chan_to_owner(struct dma_chan *chan)
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{
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return chan->device->dev->driver->owner;
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}
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/**
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* balance_ref_count - catch up the channel reference count
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* @chan - channel to balance ->client_count versus dmaengine_ref_count
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*
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* balance_ref_count must be called under dma_list_mutex
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*/
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static void balance_ref_count(struct dma_chan *chan)
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{
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struct module *owner = dma_chan_to_owner(chan);
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while (chan->client_count < dmaengine_ref_count) {
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__module_get(owner);
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chan->client_count++;
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}
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}
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/**
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* dma_chan_get - try to grab a dma channel's parent driver module
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* @chan - channel to grab
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*
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* Must be called under dma_list_mutex
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*/
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static int dma_chan_get(struct dma_chan *chan)
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{
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int err = -ENODEV;
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struct module *owner = dma_chan_to_owner(chan);
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if (chan->client_count) {
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__module_get(owner);
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err = 0;
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} else if (try_module_get(owner))
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err = 0;
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if (err == 0)
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chan->client_count++;
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/* allocate upon first client reference */
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if (chan->client_count == 1 && err == 0) {
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int desc_cnt = chan->device->device_alloc_chan_resources(chan);
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if (desc_cnt < 0) {
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err = desc_cnt;
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chan->client_count = 0;
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module_put(owner);
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} else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
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balance_ref_count(chan);
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}
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return err;
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}
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/**
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* dma_chan_put - drop a reference to a dma channel's parent driver module
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* @chan - channel to release
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*
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* Must be called under dma_list_mutex
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*/
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static void dma_chan_put(struct dma_chan *chan)
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{
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if (!chan->client_count)
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return; /* this channel failed alloc_chan_resources */
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chan->client_count--;
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module_put(dma_chan_to_owner(chan));
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if (chan->client_count == 0)
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chan->device->device_free_chan_resources(chan);
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}
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enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
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{
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enum dma_status status;
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unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
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dma_async_issue_pending(chan);
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do {
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status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
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if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
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printk(KERN_ERR "dma_sync_wait_timeout!\n");
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return DMA_ERROR;
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}
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} while (status == DMA_IN_PROGRESS);
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return status;
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}
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EXPORT_SYMBOL(dma_sync_wait);
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/**
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* dma_cap_mask_all - enable iteration over all operation types
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*/
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static dma_cap_mask_t dma_cap_mask_all;
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/**
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* dma_chan_tbl_ent - tracks channel allocations per core/operation
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* @chan - associated channel for this entry
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*/
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struct dma_chan_tbl_ent {
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struct dma_chan *chan;
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};
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/**
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* channel_table - percpu lookup table for memory-to-memory offload providers
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*/
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static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
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static int __init dma_channel_table_init(void)
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{
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enum dma_transaction_type cap;
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int err = 0;
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bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
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/* 'interrupt', 'private', and 'slave' are channel capabilities,
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* but are not associated with an operation so they do not need
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* an entry in the channel_table
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*/
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clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
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clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
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clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
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for_each_dma_cap_mask(cap, dma_cap_mask_all) {
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channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
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if (!channel_table[cap]) {
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err = -ENOMEM;
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break;
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}
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}
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if (err) {
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pr_err("dmaengine: initialization failure\n");
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for_each_dma_cap_mask(cap, dma_cap_mask_all)
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if (channel_table[cap])
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free_percpu(channel_table[cap]);
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}
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return err;
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}
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arch_initcall(dma_channel_table_init);
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/**
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* dma_find_channel - find a channel to carry out the operation
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* @tx_type: transaction type
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*/
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struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
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{
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return this_cpu_read(channel_table[tx_type]->chan);
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}
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EXPORT_SYMBOL(dma_find_channel);
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/*
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* net_dma_find_channel - find a channel for net_dma
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* net_dma has alignment requirements
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*/
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struct dma_chan *net_dma_find_channel(void)
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{
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struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
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if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
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return NULL;
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return chan;
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}
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EXPORT_SYMBOL(net_dma_find_channel);
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/**
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* dma_issue_pending_all - flush all pending operations across all channels
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*/
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void dma_issue_pending_all(void)
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{
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struct dma_device *device;
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struct dma_chan *chan;
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rcu_read_lock();
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list_for_each_entry_rcu(device, &dma_device_list, global_node) {
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if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
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continue;
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list_for_each_entry(chan, &device->channels, device_node)
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if (chan->client_count)
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device->device_issue_pending(chan);
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}
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rcu_read_unlock();
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}
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EXPORT_SYMBOL(dma_issue_pending_all);
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/**
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* nth_chan - returns the nth channel of the given capability
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* @cap: capability to match
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* @n: nth channel desired
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*
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* Defaults to returning the channel with the desired capability and the
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* lowest reference count when 'n' cannot be satisfied. Must be called
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* under dma_list_mutex.
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*/
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static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
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{
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struct dma_device *device;
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struct dma_chan *chan;
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struct dma_chan *ret = NULL;
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struct dma_chan *min = NULL;
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list_for_each_entry(device, &dma_device_list, global_node) {
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if (!dma_has_cap(cap, device->cap_mask) ||
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dma_has_cap(DMA_PRIVATE, device->cap_mask))
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continue;
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list_for_each_entry(chan, &device->channels, device_node) {
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if (!chan->client_count)
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continue;
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if (!min)
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min = chan;
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else if (chan->table_count < min->table_count)
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min = chan;
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if (n-- == 0) {
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ret = chan;
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break; /* done */
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}
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}
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if (ret)
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break; /* done */
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}
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if (!ret)
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ret = min;
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if (ret)
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ret->table_count++;
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return ret;
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}
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/**
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* dma_channel_rebalance - redistribute the available channels
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*
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* Optimize for cpu isolation (each cpu gets a dedicated channel for an
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* operation type) in the SMP case, and operation isolation (avoid
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* multi-tasking channels) in the non-SMP case. Must be called under
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* dma_list_mutex.
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*/
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static void dma_channel_rebalance(void)
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{
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struct dma_chan *chan;
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struct dma_device *device;
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int cpu;
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int cap;
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int n;
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/* undo the last distribution */
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for_each_dma_cap_mask(cap, dma_cap_mask_all)
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for_each_possible_cpu(cpu)
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per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
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list_for_each_entry(device, &dma_device_list, global_node) {
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if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
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continue;
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list_for_each_entry(chan, &device->channels, device_node)
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chan->table_count = 0;
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}
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|
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/* don't populate the channel_table if no clients are available */
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if (!dmaengine_ref_count)
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return;
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/* redistribute available channels */
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n = 0;
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for_each_dma_cap_mask(cap, dma_cap_mask_all)
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for_each_online_cpu(cpu) {
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if (num_possible_cpus() > 1)
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chan = nth_chan(cap, n++);
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else
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chan = nth_chan(cap, -1);
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per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
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}
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}
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|
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static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
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dma_filter_fn fn, void *fn_param)
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|
{
|
|
struct dma_chan *chan;
|
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|
|
if (!__dma_device_satisfies_mask(dev, mask)) {
|
|
pr_debug("%s: wrong capabilities\n", __func__);
|
|
return NULL;
|
|
}
|
|
/* devices with multiple channels need special handling as we need to
|
|
* ensure that all channels are either private or public.
|
|
*/
|
|
if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
|
|
list_for_each_entry(chan, &dev->channels, device_node) {
|
|
/* some channels are already publicly allocated */
|
|
if (chan->client_count)
|
|
return NULL;
|
|
}
|
|
|
|
list_for_each_entry(chan, &dev->channels, device_node) {
|
|
if (chan->client_count) {
|
|
pr_debug("%s: %s busy\n",
|
|
__func__, dma_chan_name(chan));
|
|
continue;
|
|
}
|
|
if (fn && !fn(chan, fn_param)) {
|
|
pr_debug("%s: %s filter said false\n",
|
|
__func__, dma_chan_name(chan));
|
|
continue;
|
|
}
|
|
return chan;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* dma_request_channel - try to allocate an exclusive channel
|
|
* @mask: capabilities that the channel must satisfy
|
|
* @fn: optional callback to disposition available channels
|
|
* @fn_param: opaque parameter to pass to dma_filter_fn
|
|
*/
|
|
struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
|
|
{
|
|
struct dma_device *device, *_d;
|
|
struct dma_chan *chan = NULL;
|
|
int err;
|
|
|
|
/* Find a channel */
|
|
mutex_lock(&dma_list_mutex);
|
|
list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
|
|
chan = private_candidate(mask, device, fn, fn_param);
|
|
if (chan) {
|
|
/* Found a suitable channel, try to grab, prep, and
|
|
* return it. We first set DMA_PRIVATE to disable
|
|
* balance_ref_count as this channel will not be
|
|
* published in the general-purpose allocator
|
|
*/
|
|
dma_cap_set(DMA_PRIVATE, device->cap_mask);
|
|
device->privatecnt++;
|
|
err = dma_chan_get(chan);
|
|
|
|
if (err == -ENODEV) {
|
|
pr_debug("%s: %s module removed\n", __func__,
|
|
dma_chan_name(chan));
|
|
list_del_rcu(&device->global_node);
|
|
} else if (err)
|
|
pr_debug("%s: failed to get %s: (%d)\n",
|
|
__func__, dma_chan_name(chan), err);
|
|
else
|
|
break;
|
|
if (--device->privatecnt == 0)
|
|
dma_cap_clear(DMA_PRIVATE, device->cap_mask);
|
|
chan = NULL;
|
|
}
|
|
}
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
|
|
chan ? dma_chan_name(chan) : NULL);
|
|
|
|
return chan;
|
|
}
|
|
EXPORT_SYMBOL_GPL(__dma_request_channel);
|
|
|
|
void dma_release_channel(struct dma_chan *chan)
|
|
{
|
|
mutex_lock(&dma_list_mutex);
|
|
WARN_ONCE(chan->client_count != 1,
|
|
"chan reference count %d != 1\n", chan->client_count);
|
|
dma_chan_put(chan);
|
|
/* drop PRIVATE cap enabled by __dma_request_channel() */
|
|
if (--chan->device->privatecnt == 0)
|
|
dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
|
|
mutex_unlock(&dma_list_mutex);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dma_release_channel);
|
|
|
|
/**
|
|
* dmaengine_get - register interest in dma_channels
|
|
*/
|
|
void dmaengine_get(void)
|
|
{
|
|
struct dma_device *device, *_d;
|
|
struct dma_chan *chan;
|
|
int err;
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
dmaengine_ref_count++;
|
|
|
|
/* try to grab channels */
|
|
list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
|
|
if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
|
|
continue;
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
err = dma_chan_get(chan);
|
|
if (err == -ENODEV) {
|
|
/* module removed before we could use it */
|
|
list_del_rcu(&device->global_node);
|
|
break;
|
|
} else if (err)
|
|
pr_err("%s: failed to get %s: (%d)\n",
|
|
__func__, dma_chan_name(chan), err);
|
|
}
|
|
}
|
|
|
|
/* if this is the first reference and there were channels
|
|
* waiting we need to rebalance to get those channels
|
|
* incorporated into the channel table
|
|
*/
|
|
if (dmaengine_ref_count == 1)
|
|
dma_channel_rebalance();
|
|
mutex_unlock(&dma_list_mutex);
|
|
}
|
|
EXPORT_SYMBOL(dmaengine_get);
|
|
|
|
/**
|
|
* dmaengine_put - let dma drivers be removed when ref_count == 0
|
|
*/
|
|
void dmaengine_put(void)
|
|
{
|
|
struct dma_device *device;
|
|
struct dma_chan *chan;
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
dmaengine_ref_count--;
|
|
BUG_ON(dmaengine_ref_count < 0);
|
|
/* drop channel references */
|
|
list_for_each_entry(device, &dma_device_list, global_node) {
|
|
if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
|
|
continue;
|
|
list_for_each_entry(chan, &device->channels, device_node)
|
|
dma_chan_put(chan);
|
|
}
|
|
mutex_unlock(&dma_list_mutex);
|
|
}
|
|
EXPORT_SYMBOL(dmaengine_put);
|
|
|
|
static bool device_has_all_tx_types(struct dma_device *device)
|
|
{
|
|
/* A device that satisfies this test has channels that will never cause
|
|
* an async_tx channel switch event as all possible operation types can
|
|
* be handled.
|
|
*/
|
|
#ifdef CONFIG_ASYNC_TX_DMA
|
|
if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
|
|
return false;
|
|
#endif
|
|
|
|
#if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
|
|
if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
|
|
return false;
|
|
#endif
|
|
|
|
#if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
|
|
if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
|
|
return false;
|
|
#endif
|
|
|
|
#if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
|
|
if (!dma_has_cap(DMA_XOR, device->cap_mask))
|
|
return false;
|
|
|
|
#ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
|
|
if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
|
|
return false;
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
|
|
if (!dma_has_cap(DMA_PQ, device->cap_mask))
|
|
return false;
|
|
|
|
#ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
|
|
if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
|
|
return false;
|
|
#endif
|
|
#endif
|
|
|
|
return true;
|
|
}
|
|
|
|
static int get_dma_id(struct dma_device *device)
|
|
{
|
|
int rc;
|
|
|
|
idr_retry:
|
|
if (!idr_pre_get(&dma_idr, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
mutex_lock(&dma_list_mutex);
|
|
rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
|
|
mutex_unlock(&dma_list_mutex);
|
|
if (rc == -EAGAIN)
|
|
goto idr_retry;
|
|
else if (rc != 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* dma_async_device_register - registers DMA devices found
|
|
* @device: &dma_device
|
|
*/
|
|
int dma_async_device_register(struct dma_device *device)
|
|
{
|
|
int chancnt = 0, rc;
|
|
struct dma_chan* chan;
|
|
atomic_t *idr_ref;
|
|
|
|
if (!device)
|
|
return -ENODEV;
|
|
|
|
/* validate device routines */
|
|
BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
|
|
!device->device_prep_dma_memcpy);
|
|
BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
|
|
!device->device_prep_dma_xor);
|
|
BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
|
|
!device->device_prep_dma_xor_val);
|
|
BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
|
|
!device->device_prep_dma_pq);
|
|
BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
|
|
!device->device_prep_dma_pq_val);
|
|
BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
|
|
!device->device_prep_dma_memset);
|
|
BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
|
|
!device->device_prep_dma_interrupt);
|
|
BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
|
|
!device->device_prep_dma_sg);
|
|
BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
|
|
!device->device_prep_dma_cyclic);
|
|
BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
|
|
!device->device_control);
|
|
BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
|
|
!device->device_prep_interleaved_dma);
|
|
|
|
BUG_ON(!device->device_alloc_chan_resources);
|
|
BUG_ON(!device->device_free_chan_resources);
|
|
BUG_ON(!device->device_tx_status);
|
|
BUG_ON(!device->device_issue_pending);
|
|
BUG_ON(!device->dev);
|
|
|
|
/* note: this only matters in the
|
|
* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
|
|
*/
|
|
if (device_has_all_tx_types(device))
|
|
dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
|
|
|
|
idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
|
|
if (!idr_ref)
|
|
return -ENOMEM;
|
|
rc = get_dma_id(device);
|
|
if (rc != 0) {
|
|
kfree(idr_ref);
|
|
return rc;
|
|
}
|
|
|
|
atomic_set(idr_ref, 0);
|
|
|
|
/* represent channels in sysfs. Probably want devs too */
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
rc = -ENOMEM;
|
|
chan->local = alloc_percpu(typeof(*chan->local));
|
|
if (chan->local == NULL)
|
|
goto err_out;
|
|
chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
|
|
if (chan->dev == NULL) {
|
|
free_percpu(chan->local);
|
|
chan->local = NULL;
|
|
goto err_out;
|
|
}
|
|
|
|
chan->chan_id = chancnt++;
|
|
chan->dev->device.class = &dma_devclass;
|
|
chan->dev->device.parent = device->dev;
|
|
chan->dev->chan = chan;
|
|
chan->dev->idr_ref = idr_ref;
|
|
chan->dev->dev_id = device->dev_id;
|
|
atomic_inc(idr_ref);
|
|
dev_set_name(&chan->dev->device, "dma%dchan%d",
|
|
device->dev_id, chan->chan_id);
|
|
|
|
rc = device_register(&chan->dev->device);
|
|
if (rc) {
|
|
free_percpu(chan->local);
|
|
chan->local = NULL;
|
|
kfree(chan->dev);
|
|
atomic_dec(idr_ref);
|
|
goto err_out;
|
|
}
|
|
chan->client_count = 0;
|
|
}
|
|
device->chancnt = chancnt;
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
/* take references on public channels */
|
|
if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
/* if clients are already waiting for channels we need
|
|
* to take references on their behalf
|
|
*/
|
|
if (dma_chan_get(chan) == -ENODEV) {
|
|
/* note we can only get here for the first
|
|
* channel as the remaining channels are
|
|
* guaranteed to get a reference
|
|
*/
|
|
rc = -ENODEV;
|
|
mutex_unlock(&dma_list_mutex);
|
|
goto err_out;
|
|
}
|
|
}
|
|
list_add_tail_rcu(&device->global_node, &dma_device_list);
|
|
if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
|
|
device->privatecnt++; /* Always private */
|
|
dma_channel_rebalance();
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
/* if we never registered a channel just release the idr */
|
|
if (atomic_read(idr_ref) == 0) {
|
|
mutex_lock(&dma_list_mutex);
|
|
idr_remove(&dma_idr, device->dev_id);
|
|
mutex_unlock(&dma_list_mutex);
|
|
kfree(idr_ref);
|
|
return rc;
|
|
}
|
|
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
if (chan->local == NULL)
|
|
continue;
|
|
mutex_lock(&dma_list_mutex);
|
|
chan->dev->chan = NULL;
|
|
mutex_unlock(&dma_list_mutex);
|
|
device_unregister(&chan->dev->device);
|
|
free_percpu(chan->local);
|
|
}
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL(dma_async_device_register);
|
|
|
|
/**
|
|
* dma_async_device_unregister - unregister a DMA device
|
|
* @device: &dma_device
|
|
*
|
|
* This routine is called by dma driver exit routines, dmaengine holds module
|
|
* references to prevent it being called while channels are in use.
|
|
*/
|
|
void dma_async_device_unregister(struct dma_device *device)
|
|
{
|
|
struct dma_chan *chan;
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
list_del_rcu(&device->global_node);
|
|
dma_channel_rebalance();
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
WARN_ONCE(chan->client_count,
|
|
"%s called while %d clients hold a reference\n",
|
|
__func__, chan->client_count);
|
|
mutex_lock(&dma_list_mutex);
|
|
chan->dev->chan = NULL;
|
|
mutex_unlock(&dma_list_mutex);
|
|
device_unregister(&chan->dev->device);
|
|
free_percpu(chan->local);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(dma_async_device_unregister);
|
|
|
|
/**
|
|
* dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
|
|
* @chan: DMA channel to offload copy to
|
|
* @dest: destination address (virtual)
|
|
* @src: source address (virtual)
|
|
* @len: length
|
|
*
|
|
* Both @dest and @src must be mappable to a bus address according to the
|
|
* DMA mapping API rules for streaming mappings.
|
|
* Both @dest and @src must stay memory resident (kernel memory or locked
|
|
* user space pages).
|
|
*/
|
|
dma_cookie_t
|
|
dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
|
|
void *src, size_t len)
|
|
{
|
|
struct dma_device *dev = chan->device;
|
|
struct dma_async_tx_descriptor *tx;
|
|
dma_addr_t dma_dest, dma_src;
|
|
dma_cookie_t cookie;
|
|
unsigned long flags;
|
|
|
|
dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
|
|
dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
|
|
flags = DMA_CTRL_ACK |
|
|
DMA_COMPL_SRC_UNMAP_SINGLE |
|
|
DMA_COMPL_DEST_UNMAP_SINGLE;
|
|
tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
|
|
|
|
if (!tx) {
|
|
dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
|
|
dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
tx->callback = NULL;
|
|
cookie = tx->tx_submit(tx);
|
|
|
|
preempt_disable();
|
|
__this_cpu_add(chan->local->bytes_transferred, len);
|
|
__this_cpu_inc(chan->local->memcpy_count);
|
|
preempt_enable();
|
|
|
|
return cookie;
|
|
}
|
|
EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
|
|
|
|
/**
|
|
* dma_async_memcpy_buf_to_pg - offloaded copy from address to page
|
|
* @chan: DMA channel to offload copy to
|
|
* @page: destination page
|
|
* @offset: offset in page to copy to
|
|
* @kdata: source address (virtual)
|
|
* @len: length
|
|
*
|
|
* Both @page/@offset and @kdata must be mappable to a bus address according
|
|
* to the DMA mapping API rules for streaming mappings.
|
|
* Both @page/@offset and @kdata must stay memory resident (kernel memory or
|
|
* locked user space pages)
|
|
*/
|
|
dma_cookie_t
|
|
dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
|
|
unsigned int offset, void *kdata, size_t len)
|
|
{
|
|
struct dma_device *dev = chan->device;
|
|
struct dma_async_tx_descriptor *tx;
|
|
dma_addr_t dma_dest, dma_src;
|
|
dma_cookie_t cookie;
|
|
unsigned long flags;
|
|
|
|
dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
|
|
dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
|
|
flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
|
|
tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
|
|
|
|
if (!tx) {
|
|
dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
|
|
dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
tx->callback = NULL;
|
|
cookie = tx->tx_submit(tx);
|
|
|
|
preempt_disable();
|
|
__this_cpu_add(chan->local->bytes_transferred, len);
|
|
__this_cpu_inc(chan->local->memcpy_count);
|
|
preempt_enable();
|
|
|
|
return cookie;
|
|
}
|
|
EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
|
|
|
|
/**
|
|
* dma_async_memcpy_pg_to_pg - offloaded copy from page to page
|
|
* @chan: DMA channel to offload copy to
|
|
* @dest_pg: destination page
|
|
* @dest_off: offset in page to copy to
|
|
* @src_pg: source page
|
|
* @src_off: offset in page to copy from
|
|
* @len: length
|
|
*
|
|
* Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
|
|
* address according to the DMA mapping API rules for streaming mappings.
|
|
* Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
|
|
* (kernel memory or locked user space pages).
|
|
*/
|
|
dma_cookie_t
|
|
dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
|
|
unsigned int dest_off, struct page *src_pg, unsigned int src_off,
|
|
size_t len)
|
|
{
|
|
struct dma_device *dev = chan->device;
|
|
struct dma_async_tx_descriptor *tx;
|
|
dma_addr_t dma_dest, dma_src;
|
|
dma_cookie_t cookie;
|
|
unsigned long flags;
|
|
|
|
dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
|
|
dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
|
|
DMA_FROM_DEVICE);
|
|
flags = DMA_CTRL_ACK;
|
|
tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
|
|
|
|
if (!tx) {
|
|
dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
|
|
dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
tx->callback = NULL;
|
|
cookie = tx->tx_submit(tx);
|
|
|
|
preempt_disable();
|
|
__this_cpu_add(chan->local->bytes_transferred, len);
|
|
__this_cpu_inc(chan->local->memcpy_count);
|
|
preempt_enable();
|
|
|
|
return cookie;
|
|
}
|
|
EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
|
|
|
|
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
|
|
struct dma_chan *chan)
|
|
{
|
|
tx->chan = chan;
|
|
#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
|
spin_lock_init(&tx->lock);
|
|
#endif
|
|
}
|
|
EXPORT_SYMBOL(dma_async_tx_descriptor_init);
|
|
|
|
/* dma_wait_for_async_tx - spin wait for a transaction to complete
|
|
* @tx: in-flight transaction to wait on
|
|
*/
|
|
enum dma_status
|
|
dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
|
|
|
|
if (!tx)
|
|
return DMA_SUCCESS;
|
|
|
|
while (tx->cookie == -EBUSY) {
|
|
if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
|
|
pr_err("%s timeout waiting for descriptor submission\n",
|
|
__func__);
|
|
return DMA_ERROR;
|
|
}
|
|
cpu_relax();
|
|
}
|
|
return dma_sync_wait(tx->chan, tx->cookie);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
|
|
|
|
/* dma_run_dependencies - helper routine for dma drivers to process
|
|
* (start) dependent operations on their target channel
|
|
* @tx: transaction with dependencies
|
|
*/
|
|
void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
struct dma_async_tx_descriptor *dep = txd_next(tx);
|
|
struct dma_async_tx_descriptor *dep_next;
|
|
struct dma_chan *chan;
|
|
|
|
if (!dep)
|
|
return;
|
|
|
|
/* we'll submit tx->next now, so clear the link */
|
|
txd_clear_next(tx);
|
|
chan = dep->chan;
|
|
|
|
/* keep submitting up until a channel switch is detected
|
|
* in that case we will be called again as a result of
|
|
* processing the interrupt from async_tx_channel_switch
|
|
*/
|
|
for (; dep; dep = dep_next) {
|
|
txd_lock(dep);
|
|
txd_clear_parent(dep);
|
|
dep_next = txd_next(dep);
|
|
if (dep_next && dep_next->chan == chan)
|
|
txd_clear_next(dep); /* ->next will be submitted */
|
|
else
|
|
dep_next = NULL; /* submit current dep and terminate */
|
|
txd_unlock(dep);
|
|
|
|
dep->tx_submit(dep);
|
|
}
|
|
|
|
chan->device->device_issue_pending(chan);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dma_run_dependencies);
|
|
|
|
static int __init dma_bus_init(void)
|
|
{
|
|
return class_register(&dma_devclass);
|
|
}
|
|
arch_initcall(dma_bus_init);
|
|
|
|
|