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02c587733c
CONFIG_KASAN_STACK and CONFIG_KASAN_STACK_ENABLE both enable KASAN stack
instrumentation, but we should only need one config, so that we remove
CONFIG_KASAN_STACK_ENABLE and make CONFIG_KASAN_STACK workable. see [1].
When enable KASAN stack instrumentation, then for gcc we could do no
prompt and default value y, and for clang prompt and default value n.
This patch fixes the following compilation warning:
include/linux/kasan.h:333:30: warning: 'CONFIG_KASAN_STACK' is not defined, evaluates to 0 [-Wundef]
[akpm@linux-foundation.org: fix merge snafu]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=210221 [1]
Link: https://lkml.kernel.org/r/20210226012531.29231-1-walter-zh.wu@mediatek.com
Fixes: d9b571c885
("kasan: fix KASAN_STACK dependency for HW_TAGS")
Signed-off-by: Walter Wu <walter-zh.wu@mediatek.com>
Suggested-by: Dmitry Vyukov <dvyukov@google.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Andrey Konovalov <andreyknvl@google.com>
Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Alexander Potapenko <glider@google.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
151 lines
4.5 KiB
ArmAsm
151 lines
4.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/smp.h>
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.text
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/*
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* Implementation of MPIDR_EL1 hash algorithm through shifting
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* and OR'ing.
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*
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* @dst: register containing hash result
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* @rs0: register containing affinity level 0 bit shift
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* @rs1: register containing affinity level 1 bit shift
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* @rs2: register containing affinity level 2 bit shift
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* @rs3: register containing affinity level 3 bit shift
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* @mpidr: register containing MPIDR_EL1 value
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* @mask: register containing MPIDR mask
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*
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* Pseudo C-code:
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*
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*u32 dst;
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*
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*compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
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* u32 aff0, aff1, aff2, aff3;
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* u64 mpidr_masked = mpidr & mask;
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* aff0 = mpidr_masked & 0xff;
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* aff1 = mpidr_masked & 0xff00;
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* aff2 = mpidr_masked & 0xff0000;
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* aff3 = mpidr_masked & 0xff00000000;
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* dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
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*}
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* Input registers: rs0, rs1, rs2, rs3, mpidr, mask
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* Output register: dst
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* Note: input and output registers must be disjoint register sets
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(eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
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*/
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.macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
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and \mpidr, \mpidr, \mask // mask out MPIDR bits
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and \dst, \mpidr, #0xff // mask=aff0
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lsr \dst ,\dst, \rs0 // dst=aff0>>rs0
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and \mask, \mpidr, #0xff00 // mask = aff1
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lsr \mask ,\mask, \rs1
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orr \dst, \dst, \mask // dst|=(aff1>>rs1)
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and \mask, \mpidr, #0xff0000 // mask = aff2
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lsr \mask ,\mask, \rs2
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orr \dst, \dst, \mask // dst|=(aff2>>rs2)
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and \mask, \mpidr, #0xff00000000 // mask = aff3
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lsr \mask ,\mask, \rs3
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orr \dst, \dst, \mask // dst|=(aff3>>rs3)
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.endm
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/*
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* Save CPU state in the provided sleep_stack_data area, and publish its
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* location for cpu_resume()'s use in sleep_save_stash.
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*
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* cpu_resume() will restore this saved state, and return. Because the
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* link-register is saved and restored, it will appear to return from this
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* function. So that the caller can tell the suspend/resume paths apart,
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* __cpu_suspend_enter() will always return a non-zero value, whereas the
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* path through cpu_resume() will return 0.
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*
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* x0 = struct sleep_stack_data area
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*/
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SYM_FUNC_START(__cpu_suspend_enter)
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stp x29, lr, [x0, #SLEEP_STACK_DATA_CALLEE_REGS]
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stp x19, x20, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+16]
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stp x21, x22, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+32]
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stp x23, x24, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+48]
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stp x25, x26, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+64]
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stp x27, x28, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+80]
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/* save the sp in cpu_suspend_ctx */
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mov x2, sp
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str x2, [x0, #SLEEP_STACK_DATA_SYSTEM_REGS + CPU_CTX_SP]
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/* find the mpidr_hash */
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ldr_l x1, sleep_save_stash
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mrs x7, mpidr_el1
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adr_l x9, mpidr_hash
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ldr x10, [x9, #MPIDR_HASH_MASK]
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/*
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* Following code relies on the struct mpidr_hash
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* members size.
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*/
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ldp w3, w4, [x9, #MPIDR_HASH_SHIFTS]
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ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
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compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
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add x1, x1, x8, lsl #3
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str x0, [x1]
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add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
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stp x29, lr, [sp, #-16]!
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bl cpu_do_suspend
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ldp x29, lr, [sp], #16
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mov x0, #1
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ret
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SYM_FUNC_END(__cpu_suspend_enter)
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.pushsection ".idmap.text", "awx"
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SYM_CODE_START(cpu_resume)
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bl init_kernel_el
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bl switch_to_vhe
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bl __cpu_setup
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/* enable the MMU early - so we can access sleep_save_stash by va */
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adrp x1, swapper_pg_dir
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bl __enable_mmu
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ldr x8, =_cpu_resume
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br x8
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SYM_CODE_END(cpu_resume)
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.ltorg
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.popsection
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SYM_FUNC_START(_cpu_resume)
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mrs x1, mpidr_el1
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adr_l x8, mpidr_hash // x8 = struct mpidr_hash virt address
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/* retrieve mpidr_hash members to compute the hash */
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ldr x2, [x8, #MPIDR_HASH_MASK]
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ldp w3, w4, [x8, #MPIDR_HASH_SHIFTS]
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ldp w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)]
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compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2
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/* x7 contains hash index, let's use it to grab context pointer */
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ldr_l x0, sleep_save_stash
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ldr x0, [x0, x7, lsl #3]
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add x29, x0, #SLEEP_STACK_DATA_CALLEE_REGS
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add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
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/* load sp from context */
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ldr x2, [x0, #CPU_CTX_SP]
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mov sp, x2
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/*
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* cpu_do_resume expects x0 to contain context address pointer
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*/
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bl cpu_do_resume
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#if defined(CONFIG_KASAN) && defined(CONFIG_KASAN_STACK)
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mov x0, sp
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bl kasan_unpoison_task_stack_below
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#endif
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ldp x19, x20, [x29, #16]
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ldp x21, x22, [x29, #32]
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ldp x23, x24, [x29, #48]
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ldp x25, x26, [x29, #64]
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ldp x27, x28, [x29, #80]
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ldp x29, lr, [x29]
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mov x0, #0
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ret
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SYM_FUNC_END(_cpu_resume)
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