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ec63e300fa
The current code to print PSTATE when generating backtraces does not include SSBS bit and DIT bit, so add this information. Cc: Vladimir Murzin <vladimir.murzin@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Lingyan Huang <huanglingyan2@huawei.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/1626920436-54816-1-git-send-email-zhangshaokun@hisilicon.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
710 lines
18 KiB
C
710 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on arch/arm/kernel/process.c
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*
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* Original Copyright (C) 1995 Linus Torvalds
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* Copyright (C) 1996-2000 Russell King - Converted to ARM.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <stdarg.h>
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#include <linux/compat.h>
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#include <linux/efi.h>
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#include <linux/elf.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/kernel.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/nospec.h>
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#include <linux/stddef.h>
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#include <linux/sysctl.h>
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#include <linux/unistd.h>
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#include <linux/user.h>
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#include <linux/delay.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/elfcore.h>
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#include <linux/pm.h>
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#include <linux/tick.h>
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#include <linux/utsname.h>
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#include <linux/uaccess.h>
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#include <linux/random.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/personality.h>
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#include <linux/notifier.h>
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#include <trace/events/power.h>
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#include <linux/percpu.h>
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#include <linux/thread_info.h>
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#include <linux/prctl.h>
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#include <asm/alternative.h>
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#include <asm/compat.h>
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#include <asm/cpufeature.h>
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#include <asm/cacheflush.h>
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#include <asm/exec.h>
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#include <asm/fpsimd.h>
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#include <asm/mmu_context.h>
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#include <asm/mte.h>
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#include <asm/processor.h>
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#include <asm/pointer_auth.h>
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#include <asm/stacktrace.h>
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#include <asm/switch_to.h>
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#include <asm/system_misc.h>
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#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
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#include <linux/stackprotector.h>
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unsigned long __stack_chk_guard __read_mostly;
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EXPORT_SYMBOL(__stack_chk_guard);
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#endif
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/*
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* Function pointers to optional machine specific functions
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*/
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void (*pm_power_off)(void);
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EXPORT_SYMBOL_GPL(pm_power_off);
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#ifdef CONFIG_HOTPLUG_CPU
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void arch_cpu_idle_dead(void)
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{
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cpu_die();
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}
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#endif
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/*
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* Called by kexec, immediately prior to machine_kexec().
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*
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* This must completely disable all secondary CPUs; simply causing those CPUs
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* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
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* kexec'd kernel to use any and all RAM as it sees fit, without having to
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* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
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* functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
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*/
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void machine_shutdown(void)
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{
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smp_shutdown_nonboot_cpus(reboot_cpu);
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}
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/*
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* Halting simply requires that the secondary CPUs stop performing any
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* activity (executing tasks, handling interrupts). smp_send_stop()
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* achieves this.
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*/
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void machine_halt(void)
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{
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local_irq_disable();
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smp_send_stop();
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while (1);
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}
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/*
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* Power-off simply requires that the secondary CPUs stop performing any
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* activity (executing tasks, handling interrupts). smp_send_stop()
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* achieves this. When the system power is turned off, it will take all CPUs
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* with it.
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*/
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void machine_power_off(void)
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{
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local_irq_disable();
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smp_send_stop();
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if (pm_power_off)
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pm_power_off();
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}
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/*
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* Restart requires that the secondary CPUs stop performing any activity
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* while the primary CPU resets the system. Systems with multiple CPUs must
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* provide a HW restart implementation, to ensure that all CPUs reset at once.
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* This is required so that any code running after reset on the primary CPU
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* doesn't have to co-ordinate with other CPUs to ensure they aren't still
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* executing pre-reset code, and using RAM that the primary CPU's code wishes
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* to use. Implementing such co-ordination would be essentially impossible.
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*/
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void machine_restart(char *cmd)
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{
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/* Disable interrupts first */
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local_irq_disable();
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smp_send_stop();
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/*
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* UpdateCapsule() depends on the system being reset via
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* ResetSystem().
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*/
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if (efi_enabled(EFI_RUNTIME_SERVICES))
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efi_reboot(reboot_mode, NULL);
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/* Now call the architecture specific reboot code. */
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do_kernel_restart(cmd);
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/*
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* Whoops - the architecture was unable to reboot.
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*/
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printk("Reboot failed -- System halted\n");
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while (1);
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}
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#define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
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static const char *const btypes[] = {
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bstr(NONE, "--"),
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bstr( JC, "jc"),
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bstr( C, "-c"),
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bstr( J , "j-")
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};
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#undef bstr
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static void print_pstate(struct pt_regs *regs)
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{
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u64 pstate = regs->pstate;
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if (compat_user_mode(regs)) {
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printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c %cDIT %cSSBS)\n",
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pstate,
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pstate & PSR_AA32_N_BIT ? 'N' : 'n',
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pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
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pstate & PSR_AA32_C_BIT ? 'C' : 'c',
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pstate & PSR_AA32_V_BIT ? 'V' : 'v',
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pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
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pstate & PSR_AA32_T_BIT ? "T32" : "A32",
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pstate & PSR_AA32_E_BIT ? "BE" : "LE",
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pstate & PSR_AA32_A_BIT ? 'A' : 'a',
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pstate & PSR_AA32_I_BIT ? 'I' : 'i',
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pstate & PSR_AA32_F_BIT ? 'F' : 'f',
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pstate & PSR_AA32_DIT_BIT ? '+' : '-',
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pstate & PSR_AA32_SSBS_BIT ? '+' : '-');
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} else {
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const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
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PSR_BTYPE_SHIFT];
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printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
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pstate,
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pstate & PSR_N_BIT ? 'N' : 'n',
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pstate & PSR_Z_BIT ? 'Z' : 'z',
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pstate & PSR_C_BIT ? 'C' : 'c',
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pstate & PSR_V_BIT ? 'V' : 'v',
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pstate & PSR_D_BIT ? 'D' : 'd',
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pstate & PSR_A_BIT ? 'A' : 'a',
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pstate & PSR_I_BIT ? 'I' : 'i',
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pstate & PSR_F_BIT ? 'F' : 'f',
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pstate & PSR_PAN_BIT ? '+' : '-',
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pstate & PSR_UAO_BIT ? '+' : '-',
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pstate & PSR_TCO_BIT ? '+' : '-',
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pstate & PSR_DIT_BIT ? '+' : '-',
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pstate & PSR_SSBS_BIT ? '+' : '-',
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btype_str);
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}
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}
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void __show_regs(struct pt_regs *regs)
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{
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int i, top_reg;
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u64 lr, sp;
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if (compat_user_mode(regs)) {
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lr = regs->compat_lr;
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sp = regs->compat_sp;
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top_reg = 12;
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} else {
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lr = regs->regs[30];
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sp = regs->sp;
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top_reg = 29;
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}
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show_regs_print_info(KERN_DEFAULT);
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print_pstate(regs);
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if (!user_mode(regs)) {
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printk("pc : %pS\n", (void *)regs->pc);
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printk("lr : %pS\n", (void *)ptrauth_strip_insn_pac(lr));
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} else {
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printk("pc : %016llx\n", regs->pc);
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printk("lr : %016llx\n", lr);
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}
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printk("sp : %016llx\n", sp);
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if (system_uses_irq_prio_masking())
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printk("pmr_save: %08llx\n", regs->pmr_save);
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i = top_reg;
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while (i >= 0) {
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printk("x%-2d: %016llx", i, regs->regs[i]);
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while (i-- % 3)
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pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
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pr_cont("\n");
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}
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}
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void show_regs(struct pt_regs *regs)
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{
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__show_regs(regs);
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dump_backtrace(regs, NULL, KERN_DEFAULT);
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}
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static void tls_thread_flush(void)
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{
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write_sysreg(0, tpidr_el0);
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if (is_compat_task()) {
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current->thread.uw.tp_value = 0;
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/*
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* We need to ensure ordering between the shadow state and the
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* hardware state, so that we don't corrupt the hardware state
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* with a stale shadow state during context switch.
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*/
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barrier();
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write_sysreg(0, tpidrro_el0);
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}
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}
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static void flush_tagged_addr_state(void)
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{
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if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
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clear_thread_flag(TIF_TAGGED_ADDR);
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}
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void flush_thread(void)
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{
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fpsimd_flush_thread();
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tls_thread_flush();
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flush_ptrace_hw_breakpoint(current);
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flush_tagged_addr_state();
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}
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void release_thread(struct task_struct *dead_task)
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{
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}
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void arch_release_task_struct(struct task_struct *tsk)
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{
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fpsimd_release_task(tsk);
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}
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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if (current->mm)
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fpsimd_preserve_current_state();
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*dst = *src;
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/* We rely on the above assignment to initialize dst's thread_flags: */
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BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK));
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/*
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* Detach src's sve_state (if any) from dst so that it does not
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* get erroneously used or freed prematurely. dst's sve_state
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* will be allocated on demand later on if dst uses SVE.
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* For consistency, also clear TIF_SVE here: this could be done
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* later in copy_process(), but to avoid tripping up future
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* maintainers it is best not to leave TIF_SVE and sve_state in
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* an inconsistent state, even temporarily.
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*/
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dst->thread.sve_state = NULL;
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clear_tsk_thread_flag(dst, TIF_SVE);
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/* clear any pending asynchronous tag fault raised by the parent */
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clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
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return 0;
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}
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asmlinkage void ret_from_fork(void) asm("ret_from_fork");
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int copy_thread(unsigned long clone_flags, unsigned long stack_start,
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unsigned long stk_sz, struct task_struct *p, unsigned long tls)
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{
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struct pt_regs *childregs = task_pt_regs(p);
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memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
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/*
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* In case p was allocated the same task_struct pointer as some
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* other recently-exited task, make sure p is disassociated from
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* any cpu that may have run that now-exited task recently.
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* Otherwise we could erroneously skip reloading the FPSIMD
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* registers for p.
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*/
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fpsimd_flush_task_state(p);
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ptrauth_thread_init_kernel(p);
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if (likely(!(p->flags & (PF_KTHREAD | PF_IO_WORKER)))) {
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*childregs = *current_pt_regs();
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childregs->regs[0] = 0;
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/*
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* Read the current TLS pointer from tpidr_el0 as it may be
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* out-of-sync with the saved value.
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*/
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*task_user_tls(p) = read_sysreg(tpidr_el0);
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if (stack_start) {
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if (is_compat_thread(task_thread_info(p)))
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childregs->compat_sp = stack_start;
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else
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childregs->sp = stack_start;
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}
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/*
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* If a TLS pointer was passed to clone, use it for the new
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* thread.
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*/
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if (clone_flags & CLONE_SETTLS)
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p->thread.uw.tp_value = tls;
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} else {
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/*
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* A kthread has no context to ERET to, so ensure any buggy
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* ERET is treated as an illegal exception return.
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*
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* When a user task is created from a kthread, childregs will
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* be initialized by start_thread() or start_compat_thread().
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*/
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memset(childregs, 0, sizeof(struct pt_regs));
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childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
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p->thread.cpu_context.x19 = stack_start;
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p->thread.cpu_context.x20 = stk_sz;
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}
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p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
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p->thread.cpu_context.sp = (unsigned long)childregs;
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/*
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* For the benefit of the unwinder, set up childregs->stackframe
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* as the final frame for the new task.
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*/
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p->thread.cpu_context.fp = (unsigned long)childregs->stackframe;
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ptrace_hw_copy_thread(p);
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return 0;
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}
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void tls_preserve_current_state(void)
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{
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*task_user_tls(current) = read_sysreg(tpidr_el0);
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}
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static void tls_thread_switch(struct task_struct *next)
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{
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tls_preserve_current_state();
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if (is_compat_thread(task_thread_info(next)))
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write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
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else if (!arm64_kernel_unmapped_at_el0())
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write_sysreg(0, tpidrro_el0);
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write_sysreg(*task_user_tls(next), tpidr_el0);
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}
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/*
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* Force SSBS state on context-switch, since it may be lost after migrating
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* from a CPU which treats the bit as RES0 in a heterogeneous system.
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*/
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static void ssbs_thread_switch(struct task_struct *next)
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{
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/*
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* Nothing to do for kernel threads, but 'regs' may be junk
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* (e.g. idle task) so check the flags and bail early.
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*/
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if (unlikely(next->flags & PF_KTHREAD))
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return;
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/*
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* If all CPUs implement the SSBS extension, then we just need to
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* context-switch the PSTATE field.
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*/
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if (cpus_have_const_cap(ARM64_SSBS))
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return;
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spectre_v4_enable_task_mitigation(next);
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}
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/*
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* We store our current task in sp_el0, which is clobbered by userspace. Keep a
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* shadow copy so that we can restore this upon entry from userspace.
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*
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* This is *only* for exception entry from EL0, and is not valid until we
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* __switch_to() a user task.
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*/
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DEFINE_PER_CPU(struct task_struct *, __entry_task);
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static void entry_task_switch(struct task_struct *next)
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{
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__this_cpu_write(__entry_task, next);
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}
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/*
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* ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
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* Assuming the virtual counter is enabled at the beginning of times:
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*
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* - disable access when switching from a 64bit task to a 32bit task
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* - enable access when switching from a 32bit task to a 64bit task
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*/
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static void erratum_1418040_thread_switch(struct task_struct *prev,
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struct task_struct *next)
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{
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bool prev32, next32;
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u64 val;
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040))
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return;
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prev32 = is_compat_thread(task_thread_info(prev));
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next32 = is_compat_thread(task_thread_info(next));
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if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
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return;
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val = read_sysreg(cntkctl_el1);
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if (!next32)
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val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
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else
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val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
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write_sysreg(val, cntkctl_el1);
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}
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static void compat_thread_switch(struct task_struct *next)
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{
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if (!is_compat_thread(task_thread_info(next)))
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return;
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if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
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set_tsk_thread_flag(next, TIF_NOTIFY_RESUME);
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}
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static void update_sctlr_el1(u64 sctlr)
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{
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|
/*
|
|
* EnIA must not be cleared while in the kernel as this is necessary for
|
|
* in-kernel PAC. It will be cleared on kernel exit if needed.
|
|
*/
|
|
sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
|
|
|
|
/* ISB required for the kernel uaccess routines when setting TCF0. */
|
|
isb();
|
|
}
|
|
|
|
void set_task_sctlr_el1(u64 sctlr)
|
|
{
|
|
/*
|
|
* __switch_to() checks current->thread.sctlr as an
|
|
* optimisation. Disable preemption so that it does not see
|
|
* the variable update before the SCTLR_EL1 one.
|
|
*/
|
|
preempt_disable();
|
|
current->thread.sctlr_user = sctlr;
|
|
update_sctlr_el1(sctlr);
|
|
preempt_enable();
|
|
}
|
|
|
|
/*
|
|
* Thread switching.
|
|
*/
|
|
__notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
|
|
struct task_struct *next)
|
|
{
|
|
struct task_struct *last;
|
|
|
|
fpsimd_thread_switch(next);
|
|
tls_thread_switch(next);
|
|
hw_breakpoint_thread_switch(next);
|
|
contextidr_thread_switch(next);
|
|
entry_task_switch(next);
|
|
ssbs_thread_switch(next);
|
|
erratum_1418040_thread_switch(prev, next);
|
|
ptrauth_thread_switch_user(next);
|
|
compat_thread_switch(next);
|
|
|
|
/*
|
|
* Complete any pending TLB or cache maintenance on this CPU in case
|
|
* the thread migrates to a different CPU.
|
|
* This full barrier is also required by the membarrier system
|
|
* call.
|
|
*/
|
|
dsb(ish);
|
|
|
|
/*
|
|
* MTE thread switching must happen after the DSB above to ensure that
|
|
* any asynchronous tag check faults have been logged in the TFSR*_EL1
|
|
* registers.
|
|
*/
|
|
mte_thread_switch(next);
|
|
/* avoid expensive SCTLR_EL1 accesses if no change */
|
|
if (prev->thread.sctlr_user != next->thread.sctlr_user)
|
|
update_sctlr_el1(next->thread.sctlr_user);
|
|
|
|
/* the actual thread switch */
|
|
last = cpu_switch_to(prev, next);
|
|
|
|
return last;
|
|
}
|
|
|
|
unsigned long get_wchan(struct task_struct *p)
|
|
{
|
|
struct stackframe frame;
|
|
unsigned long stack_page, ret = 0;
|
|
int count = 0;
|
|
if (!p || p == current || task_is_running(p))
|
|
return 0;
|
|
|
|
stack_page = (unsigned long)try_get_task_stack(p);
|
|
if (!stack_page)
|
|
return 0;
|
|
|
|
start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p));
|
|
|
|
do {
|
|
if (unwind_frame(p, &frame))
|
|
goto out;
|
|
if (!in_sched_functions(frame.pc)) {
|
|
ret = frame.pc;
|
|
goto out;
|
|
}
|
|
} while (count++ < 16);
|
|
|
|
out:
|
|
put_task_stack(p);
|
|
return ret;
|
|
}
|
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
{
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
sp -= get_random_int() & ~PAGE_MASK;
|
|
return sp & ~0xf;
|
|
}
|
|
|
|
/*
|
|
* Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
|
|
*/
|
|
void arch_setup_new_exec(void)
|
|
{
|
|
unsigned long mmflags = 0;
|
|
|
|
if (is_compat_task()) {
|
|
mmflags = MMCF_AARCH32;
|
|
if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
|
|
set_tsk_thread_flag(current, TIF_NOTIFY_RESUME);
|
|
}
|
|
|
|
current->mm->context.flags = mmflags;
|
|
ptrauth_thread_init_user();
|
|
mte_thread_init_user();
|
|
|
|
if (task_spec_ssb_noexec(current)) {
|
|
arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
|
|
PR_SPEC_ENABLE);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
|
|
/*
|
|
* Control the relaxed ABI allowing tagged user addresses into the kernel.
|
|
*/
|
|
static unsigned int tagged_addr_disabled;
|
|
|
|
long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
|
|
{
|
|
unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
|
|
struct thread_info *ti = task_thread_info(task);
|
|
|
|
if (is_compat_thread(ti))
|
|
return -EINVAL;
|
|
|
|
if (system_supports_mte())
|
|
valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK;
|
|
|
|
if (arg & ~valid_mask)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Do not allow the enabling of the tagged address ABI if globally
|
|
* disabled via sysctl abi.tagged_addr_disabled.
|
|
*/
|
|
if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
|
|
return -EINVAL;
|
|
|
|
if (set_mte_ctrl(task, arg) != 0)
|
|
return -EINVAL;
|
|
|
|
update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
long get_tagged_addr_ctrl(struct task_struct *task)
|
|
{
|
|
long ret = 0;
|
|
struct thread_info *ti = task_thread_info(task);
|
|
|
|
if (is_compat_thread(ti))
|
|
return -EINVAL;
|
|
|
|
if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
|
|
ret = PR_TAGGED_ADDR_ENABLE;
|
|
|
|
ret |= get_mte_ctrl(task);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Global sysctl to disable the tagged user addresses support. This control
|
|
* only prevents the tagged address ABI enabling via prctl() and does not
|
|
* disable it for tasks that already opted in to the relaxed ABI.
|
|
*/
|
|
|
|
static struct ctl_table tagged_addr_sysctl_table[] = {
|
|
{
|
|
.procname = "tagged_addr_disabled",
|
|
.mode = 0644,
|
|
.data = &tagged_addr_disabled,
|
|
.maxlen = sizeof(int),
|
|
.proc_handler = proc_dointvec_minmax,
|
|
.extra1 = SYSCTL_ZERO,
|
|
.extra2 = SYSCTL_ONE,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
static int __init tagged_addr_init(void)
|
|
{
|
|
if (!register_sysctl("abi", tagged_addr_sysctl_table))
|
|
return -EINVAL;
|
|
return 0;
|
|
}
|
|
|
|
core_initcall(tagged_addr_init);
|
|
#endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
|
|
|
|
#ifdef CONFIG_BINFMT_ELF
|
|
int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
|
|
bool has_interp, bool is_interp)
|
|
{
|
|
/*
|
|
* For dynamically linked executables the interpreter is
|
|
* responsible for setting PROT_BTI on everything except
|
|
* itself.
|
|
*/
|
|
if (is_interp != has_interp)
|
|
return prot;
|
|
|
|
if (!(state->flags & ARM64_ELF_BTI))
|
|
return prot;
|
|
|
|
if (prot & PROT_EXEC)
|
|
prot |= PROT_BTI;
|
|
|
|
return prot;
|
|
}
|
|
#endif
|