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59f44069e0
Since commit:bad1e1c663
("arm64: mte: switch GCR_EL1 in kernel entry and exit") we saved/restored the user GCR_EL1 value at exception boundaries, and update_gcr_el1_excl() is no longer used for this. However it is used to restore the kernel's GCR_EL1 value when returning from a suspend state. Thus, the comment is misleading (and an ISB is necessary). When restoring the kernel's GCR value, we need an ISB to ensure this is used by subsequent instructions. We don't necessarily get an ISB by other means (e.g. if the kernel is built without support for pointer authentication). As __cpu_setup() initialised GCR_EL1.Exclude to 0xffff, until a context synchronization event, allocation tag 0 may be used rather than the desired set of tags. This patch drops the misleading comment, adds the missing ISB, and for clarity folds update_gcr_el1_excl() into its only user. Fixes:bad1e1c663
("arm64: mte: switch GCR_EL1 in kernel entry and exit") Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Andrey Konovalov <andreyknvl@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Vincenzo Frascino <vincenzo.frascino@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210714143843.56537-2-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org>
453 lines
10 KiB
C
453 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 ARM Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/prctl.h>
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#include <linux/sched.h>
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#include <linux/sched/mm.h>
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#include <linux/string.h>
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#include <linux/swap.h>
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#include <linux/swapops.h>
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#include <linux/thread_info.h>
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#include <linux/types.h>
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#include <linux/uio.h>
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#include <asm/barrier.h>
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#include <asm/cpufeature.h>
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#include <asm/mte.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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u64 gcr_kernel_excl __ro_after_init;
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static bool report_fault_once = true;
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#ifdef CONFIG_KASAN_HW_TAGS
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/* Whether the MTE asynchronous mode is enabled. */
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DEFINE_STATIC_KEY_FALSE(mte_async_mode);
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EXPORT_SYMBOL_GPL(mte_async_mode);
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#endif
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static void mte_sync_page_tags(struct page *page, pte_t old_pte,
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bool check_swap, bool pte_is_tagged)
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{
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if (check_swap && is_swap_pte(old_pte)) {
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swp_entry_t entry = pte_to_swp_entry(old_pte);
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if (!non_swap_entry(entry) && mte_restore_tags(entry, page))
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return;
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}
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if (!pte_is_tagged)
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return;
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page_kasan_tag_reset(page);
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/*
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* We need smp_wmb() in between setting the flags and clearing the
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* tags because if another thread reads page->flags and builds a
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* tagged address out of it, there is an actual dependency to the
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* memory access, but on the current thread we do not guarantee that
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* the new page->flags are visible before the tags were updated.
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*/
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smp_wmb();
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mte_clear_page_tags(page_address(page));
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}
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void mte_sync_tags(pte_t old_pte, pte_t pte)
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{
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struct page *page = pte_page(pte);
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long i, nr_pages = compound_nr(page);
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bool check_swap = nr_pages == 1;
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bool pte_is_tagged = pte_tagged(pte);
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/* Early out if there's nothing to do */
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if (!check_swap && !pte_is_tagged)
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return;
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/* if PG_mte_tagged is set, tags have already been initialised */
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for (i = 0; i < nr_pages; i++, page++) {
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if (!test_and_set_bit(PG_mte_tagged, &page->flags))
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mte_sync_page_tags(page, old_pte, check_swap,
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pte_is_tagged);
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}
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}
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int memcmp_pages(struct page *page1, struct page *page2)
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{
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char *addr1, *addr2;
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int ret;
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addr1 = page_address(page1);
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addr2 = page_address(page2);
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ret = memcmp(addr1, addr2, PAGE_SIZE);
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if (!system_supports_mte() || ret)
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return ret;
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/*
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* If the page content is identical but at least one of the pages is
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* tagged, return non-zero to avoid KSM merging. If only one of the
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* pages is tagged, set_pte_at() may zero or change the tags of the
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* other page via mte_sync_tags().
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*/
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if (test_bit(PG_mte_tagged, &page1->flags) ||
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test_bit(PG_mte_tagged, &page2->flags))
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return addr1 != addr2;
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return ret;
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}
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void mte_init_tags(u64 max_tag)
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{
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static bool gcr_kernel_excl_initialized;
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if (!gcr_kernel_excl_initialized) {
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/*
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* The format of the tags in KASAN is 0xFF and in MTE is 0xF.
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* This conversion extracts an MTE tag from a KASAN tag.
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*/
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u64 incl = GENMASK(FIELD_GET(MTE_TAG_MASK >> MTE_TAG_SHIFT,
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max_tag), 0);
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gcr_kernel_excl = ~incl & SYS_GCR_EL1_EXCL_MASK;
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gcr_kernel_excl_initialized = true;
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}
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/* Enable the kernel exclude mask for random tags generation. */
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write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1);
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}
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static inline void __mte_enable_kernel(const char *mode, unsigned long tcf)
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{
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/* Enable MTE Sync Mode for EL1. */
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sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, tcf);
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isb();
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pr_info_once("MTE: enabled in %s mode at EL1\n", mode);
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}
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#ifdef CONFIG_KASAN_HW_TAGS
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void mte_enable_kernel_sync(void)
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{
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/*
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* Make sure we enter this function when no PE has set
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* async mode previously.
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*/
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WARN_ONCE(system_uses_mte_async_mode(),
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"MTE async mode enabled system wide!");
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__mte_enable_kernel("synchronous", SCTLR_ELx_TCF_SYNC);
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}
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void mte_enable_kernel_async(void)
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{
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__mte_enable_kernel("asynchronous", SCTLR_ELx_TCF_ASYNC);
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/*
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* MTE async mode is set system wide by the first PE that
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* executes this function.
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*
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* Note: If in future KASAN acquires a runtime switching
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* mode in between sync and async, this strategy needs
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* to be reviewed.
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*/
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if (!system_uses_mte_async_mode())
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static_branch_enable(&mte_async_mode);
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}
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#endif
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void mte_set_report_once(bool state)
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{
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WRITE_ONCE(report_fault_once, state);
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}
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bool mte_report_once(void)
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{
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return READ_ONCE(report_fault_once);
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}
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#ifdef CONFIG_KASAN_HW_TAGS
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void mte_check_tfsr_el1(void)
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{
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u64 tfsr_el1;
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if (!system_supports_mte())
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return;
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tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
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if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) {
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/*
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* Note: isb() is not required after this direct write
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* because there is no indirect read subsequent to it
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* (per ARM DDI 0487F.c table D13-1).
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*/
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write_sysreg_s(0, SYS_TFSR_EL1);
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kasan_report_async();
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}
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}
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#endif
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static void set_gcr_el1_excl(u64 excl)
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{
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current->thread.gcr_user_excl = excl;
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/*
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* SYS_GCR_EL1 will be set to current->thread.gcr_user_excl value
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* by mte_set_user_gcr() in kernel_exit,
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*/
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}
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void mte_thread_init_user(void)
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{
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if (!system_supports_mte())
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return;
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/* clear any pending asynchronous tag fault */
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dsb(ish);
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write_sysreg_s(0, SYS_TFSRE0_EL1);
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clear_thread_flag(TIF_MTE_ASYNC_FAULT);
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/* disable tag checking */
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set_task_sctlr_el1((current->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK) |
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SCTLR_EL1_TCF0_NONE);
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/* reset tag generation mask */
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set_gcr_el1_excl(SYS_GCR_EL1_EXCL_MASK);
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}
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void mte_thread_switch(struct task_struct *next)
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{
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/*
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* Check if an async tag exception occurred at EL1.
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*
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* Note: On the context switch path we rely on the dsb() present
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* in __switch_to() to guarantee that the indirect writes to TFSR_EL1
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* are synchronized before this point.
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*/
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isb();
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mte_check_tfsr_el1();
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}
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void mte_suspend_enter(void)
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{
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if (!system_supports_mte())
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return;
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/*
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* The barriers are required to guarantee that the indirect writes
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* to TFSR_EL1 are synchronized before we report the state.
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*/
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dsb(nsh);
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isb();
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/* Report SYS_TFSR_EL1 before suspend entry */
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mte_check_tfsr_el1();
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}
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void mte_suspend_exit(void)
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{
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if (!system_supports_mte())
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return;
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sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, gcr_kernel_excl);
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isb();
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}
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long set_mte_ctrl(struct task_struct *task, unsigned long arg)
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{
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u64 sctlr = task->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK;
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u64 gcr_excl = ~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
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SYS_GCR_EL1_EXCL_MASK;
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if (!system_supports_mte())
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return 0;
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switch (arg & PR_MTE_TCF_MASK) {
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case PR_MTE_TCF_NONE:
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sctlr |= SCTLR_EL1_TCF0_NONE;
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break;
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case PR_MTE_TCF_SYNC:
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sctlr |= SCTLR_EL1_TCF0_SYNC;
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break;
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case PR_MTE_TCF_ASYNC:
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sctlr |= SCTLR_EL1_TCF0_ASYNC;
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break;
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default:
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return -EINVAL;
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}
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if (task != current) {
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task->thread.sctlr_user = sctlr;
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task->thread.gcr_user_excl = gcr_excl;
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} else {
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set_task_sctlr_el1(sctlr);
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set_gcr_el1_excl(gcr_excl);
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}
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return 0;
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}
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long get_mte_ctrl(struct task_struct *task)
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{
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unsigned long ret;
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u64 incl = ~task->thread.gcr_user_excl & SYS_GCR_EL1_EXCL_MASK;
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if (!system_supports_mte())
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return 0;
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ret = incl << PR_MTE_TAG_SHIFT;
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switch (task->thread.sctlr_user & SCTLR_EL1_TCF0_MASK) {
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case SCTLR_EL1_TCF0_NONE:
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ret |= PR_MTE_TCF_NONE;
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break;
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case SCTLR_EL1_TCF0_SYNC:
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ret |= PR_MTE_TCF_SYNC;
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break;
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case SCTLR_EL1_TCF0_ASYNC:
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ret |= PR_MTE_TCF_ASYNC;
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break;
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}
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return ret;
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}
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/*
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* Access MTE tags in another process' address space as given in mm. Update
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* the number of tags copied. Return 0 if any tags copied, error otherwise.
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* Inspired by __access_remote_vm().
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*/
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static int __access_remote_tags(struct mm_struct *mm, unsigned long addr,
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struct iovec *kiov, unsigned int gup_flags)
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{
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struct vm_area_struct *vma;
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void __user *buf = kiov->iov_base;
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size_t len = kiov->iov_len;
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int ret;
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int write = gup_flags & FOLL_WRITE;
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if (!access_ok(buf, len))
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return -EFAULT;
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if (mmap_read_lock_killable(mm))
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return -EIO;
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while (len) {
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unsigned long tags, offset;
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void *maddr;
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struct page *page = NULL;
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ret = get_user_pages_remote(mm, addr, 1, gup_flags, &page,
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&vma, NULL);
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if (ret <= 0)
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break;
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/*
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* Only copy tags if the page has been mapped as PROT_MTE
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* (PG_mte_tagged set). Otherwise the tags are not valid and
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* not accessible to user. Moreover, an mprotect(PROT_MTE)
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* would cause the existing tags to be cleared if the page
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* was never mapped with PROT_MTE.
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*/
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if (!(vma->vm_flags & VM_MTE)) {
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ret = -EOPNOTSUPP;
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put_page(page);
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break;
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}
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WARN_ON_ONCE(!test_bit(PG_mte_tagged, &page->flags));
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/* limit access to the end of the page */
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offset = offset_in_page(addr);
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tags = min(len, (PAGE_SIZE - offset) / MTE_GRANULE_SIZE);
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maddr = page_address(page);
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if (write) {
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tags = mte_copy_tags_from_user(maddr + offset, buf, tags);
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set_page_dirty_lock(page);
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} else {
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tags = mte_copy_tags_to_user(buf, maddr + offset, tags);
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}
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put_page(page);
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/* error accessing the tracer's buffer */
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if (!tags)
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break;
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len -= tags;
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buf += tags;
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addr += tags * MTE_GRANULE_SIZE;
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}
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mmap_read_unlock(mm);
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/* return an error if no tags copied */
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kiov->iov_len = buf - kiov->iov_base;
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if (!kiov->iov_len) {
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/* check for error accessing the tracee's address space */
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if (ret <= 0)
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return -EIO;
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else
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return -EFAULT;
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}
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return 0;
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}
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/*
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* Copy MTE tags in another process' address space at 'addr' to/from tracer's
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* iovec buffer. Return 0 on success. Inspired by ptrace_access_vm().
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*/
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static int access_remote_tags(struct task_struct *tsk, unsigned long addr,
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struct iovec *kiov, unsigned int gup_flags)
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{
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struct mm_struct *mm;
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int ret;
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mm = get_task_mm(tsk);
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if (!mm)
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return -EPERM;
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if (!tsk->ptrace || (current != tsk->parent) ||
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((get_dumpable(mm) != SUID_DUMP_USER) &&
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!ptracer_capable(tsk, mm->user_ns))) {
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mmput(mm);
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return -EPERM;
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}
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ret = __access_remote_tags(mm, addr, kiov, gup_flags);
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mmput(mm);
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return ret;
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}
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int mte_ptrace_copy_tags(struct task_struct *child, long request,
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unsigned long addr, unsigned long data)
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{
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int ret;
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struct iovec kiov;
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struct iovec __user *uiov = (void __user *)data;
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unsigned int gup_flags = FOLL_FORCE;
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if (!system_supports_mte())
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return -EIO;
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if (get_user(kiov.iov_base, &uiov->iov_base) ||
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get_user(kiov.iov_len, &uiov->iov_len))
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return -EFAULT;
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if (request == PTRACE_POKEMTETAGS)
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gup_flags |= FOLL_WRITE;
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/* align addr to the MTE tag granule */
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addr &= MTE_GRANULE_MASK;
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ret = access_remote_tags(child, addr, &kiov, gup_flags);
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if (!ret)
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ret = put_user(kiov.iov_len, &uiov->iov_len);
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return ret;
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}
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