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36824f198c
- Add MTE support in guests, complete with tag save/restore interface - Reduce the impact of CMOs by moving them in the page-table code - Allow device block mappings at stage-2 - Reduce the footprint of the vmemmap in protected mode - Support the vGIC on dumb systems such as the Apple M1 - Add selftest infrastructure to support multiple configuration and apply that to PMU/non-PMU setups - Add selftests for the debug architecture - The usual crop of PMU fixes PPC: - Support for the H_RPT_INVALIDATE hypercall - Conversion of Book3S entry/exit to C - Bug fixes S390: - new HW facilities for guests - make inline assembly more robust with KASAN and co x86: - Allow userspace to handle emulation errors (unknown instructions) - Lazy allocation of the rmap (host physical -> guest physical address) - Support for virtualizing TSC scaling on VMX machines - Optimizations to avoid shattering huge pages at the beginning of live migration - Support for initializing the PDPTRs without loading them from memory - Many TLB flushing cleanups - Refuse to load if two-stage paging is available but NX is not (this has been a requirement in practice for over a year) - A large series that separates the MMU mode (WP/SMAP/SMEP etc.) from CR0/CR4/EFER, using the MMU mode everywhere once it is computed from the CPU registers - Use PM notifier to notify the guest about host suspend or hibernate - Support for passing arguments to Hyper-V hypercalls using XMM registers - Support for Hyper-V TLB flush hypercalls and enlightened MSR bitmap on AMD processors - Hide Hyper-V hypercalls that are not included in the guest CPUID - Fixes for live migration of virtual machines that use the Hyper-V "enlightened VMCS" optimization of nested virtualization - Bugfixes (not many) Generic: - Support for retrieving statistics without debugfs - Cleanups for the KVM selftests API -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmDV9UYUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroOIRgf/XX8fKLh24RnTOs2ldIu2AfRGVrT4 QMrr8MxhmtukBAszk2xKvBt8/6gkUjdaIC3xqEnVjxaDaUvZaEtP7CQlF5JV45rn iv1zyxUKucXrnIOr+gCioIT7qBlh207zV35ArKioP9Y83cWx9uAs22pfr6g+7RxO h8bJZlJbSG6IGr3voANCIb9UyjU1V/l8iEHqRwhmr/A5rARPfD7g8lfMEQeGkzX6 +/UydX2fumB3tl8e2iMQj6vLVdSOsCkehvpHK+Z33EpkKhan7GwZ2sZ05WmXV/nY QLAYfD10KegoNWl5Ay4GTp4hEAIYVrRJCLC+wnLdc0U8udbfCuTC31LK4w== =NcRh -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm updates from Paolo Bonzini: "This covers all architectures (except MIPS) so I don't expect any other feature pull requests this merge window. ARM: - Add MTE support in guests, complete with tag save/restore interface - Reduce the impact of CMOs by moving them in the page-table code - Allow device block mappings at stage-2 - Reduce the footprint of the vmemmap in protected mode - Support the vGIC on dumb systems such as the Apple M1 - Add selftest infrastructure to support multiple configuration and apply that to PMU/non-PMU setups - Add selftests for the debug architecture - The usual crop of PMU fixes PPC: - Support for the H_RPT_INVALIDATE hypercall - Conversion of Book3S entry/exit to C - Bug fixes S390: - new HW facilities for guests - make inline assembly more robust with KASAN and co x86: - Allow userspace to handle emulation errors (unknown instructions) - Lazy allocation of the rmap (host physical -> guest physical address) - Support for virtualizing TSC scaling on VMX machines - Optimizations to avoid shattering huge pages at the beginning of live migration - Support for initializing the PDPTRs without loading them from memory - Many TLB flushing cleanups - Refuse to load if two-stage paging is available but NX is not (this has been a requirement in practice for over a year) - A large series that separates the MMU mode (WP/SMAP/SMEP etc.) from CR0/CR4/EFER, using the MMU mode everywhere once it is computed from the CPU registers - Use PM notifier to notify the guest about host suspend or hibernate - Support for passing arguments to Hyper-V hypercalls using XMM registers - Support for Hyper-V TLB flush hypercalls and enlightened MSR bitmap on AMD processors - Hide Hyper-V hypercalls that are not included in the guest CPUID - Fixes for live migration of virtual machines that use the Hyper-V "enlightened VMCS" optimization of nested virtualization - Bugfixes (not many) Generic: - Support for retrieving statistics without debugfs - Cleanups for the KVM selftests API" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (314 commits) KVM: x86: rename apic_access_page_done to apic_access_memslot_enabled kvm: x86: disable the narrow guest module parameter on unload selftests: kvm: Allows userspace to handle emulation errors. kvm: x86: Allow userspace to handle emulation errors KVM: x86/mmu: Let guest use GBPAGES if supported in hardware and TDP is on KVM: x86/mmu: Get CR4.SMEP from MMU, not vCPU, in shadow page fault KVM: x86/mmu: Get CR0.WP from MMU, not vCPU, in shadow page fault KVM: x86/mmu: Drop redundant rsvd bits reset for nested NPT KVM: x86/mmu: Optimize and clean up so called "last nonleaf level" logic KVM: x86: Enhance comments for MMU roles and nested transition trickiness KVM: x86/mmu: WARN on any reserved SPTE value when making a valid SPTE KVM: x86/mmu: Add helpers to do full reserved SPTE checks w/ generic MMU KVM: x86/mmu: Use MMU's role to determine PTTYPE KVM: x86/mmu: Collapse 32-bit PAE and 64-bit statements for helpers KVM: x86/mmu: Add a helper to calculate root from role_regs KVM: x86/mmu: Add helper to update paging metadata KVM: x86/mmu: Don't update nested guest's paging bitmasks if CR0.PG=0 KVM: x86/mmu: Consolidate reset_rsvds_bits_mask() calls KVM: x86/mmu: Use MMU role_regs to get LA57, and drop vCPU LA57 helper KVM: x86/mmu: Get nested MMU's root level from the MMU's role ...
176 lines
8.2 KiB
C
176 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on arch/arm/kernel/asm-offsets.c
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*
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* Copyright (C) 1995-2003 Russell King
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* 2001-2002 Keith Owens
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <linux/arm_sdei.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/kvm_host.h>
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#include <linux/preempt.h>
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#include <linux/suspend.h>
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#include <asm/cpufeature.h>
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#include <asm/fixmap.h>
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/signal32.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <linux/kbuild.h>
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#include <linux/arm-smccc.h>
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int main(void)
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{
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DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
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DEFINE(TSK_CPU, offsetof(struct task_struct, cpu));
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BLANK();
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DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
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DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count));
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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DEFINE(TSK_TI_TTBR0, offsetof(struct task_struct, thread_info.ttbr0));
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#endif
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#ifdef CONFIG_SHADOW_CALL_STACK
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DEFINE(TSK_TI_SCS_BASE, offsetof(struct task_struct, thread_info.scs_base));
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DEFINE(TSK_TI_SCS_SP, offsetof(struct task_struct, thread_info.scs_sp));
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#endif
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DEFINE(TSK_STACK, offsetof(struct task_struct, stack));
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#ifdef CONFIG_STACKPROTECTOR
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DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
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#endif
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BLANK();
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DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
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DEFINE(THREAD_SCTLR_USER, offsetof(struct task_struct, thread.sctlr_user));
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#ifdef CONFIG_ARM64_PTR_AUTH
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DEFINE(THREAD_KEYS_USER, offsetof(struct task_struct, thread.keys_user));
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#endif
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#ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
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DEFINE(THREAD_KEYS_KERNEL, offsetof(struct task_struct, thread.keys_kernel));
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#endif
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#ifdef CONFIG_ARM64_MTE
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DEFINE(THREAD_GCR_EL1_USER, offsetof(struct task_struct, thread.gcr_user_excl));
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#endif
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BLANK();
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DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
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DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
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DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
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DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
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DEFINE(S_X8, offsetof(struct pt_regs, regs[8]));
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DEFINE(S_X10, offsetof(struct pt_regs, regs[10]));
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DEFINE(S_X12, offsetof(struct pt_regs, regs[12]));
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DEFINE(S_X14, offsetof(struct pt_regs, regs[14]));
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DEFINE(S_X16, offsetof(struct pt_regs, regs[16]));
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DEFINE(S_X18, offsetof(struct pt_regs, regs[18]));
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DEFINE(S_X20, offsetof(struct pt_regs, regs[20]));
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DEFINE(S_X22, offsetof(struct pt_regs, regs[22]));
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DEFINE(S_X24, offsetof(struct pt_regs, regs[24]));
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DEFINE(S_X26, offsetof(struct pt_regs, regs[26]));
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DEFINE(S_X28, offsetof(struct pt_regs, regs[28]));
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DEFINE(S_FP, offsetof(struct pt_regs, regs[29]));
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DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
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DEFINE(S_SP, offsetof(struct pt_regs, sp));
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DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
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DEFINE(S_PC, offsetof(struct pt_regs, pc));
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DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
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DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));
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DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));
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DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
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DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
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BLANK();
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#ifdef CONFIG_COMPAT
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DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));
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DEFINE(COMPAT_RT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_rt_sigframe, sig.uc.uc_mcontext.arm_r0));
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BLANK();
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#endif
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DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
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BLANK();
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DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
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DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
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BLANK();
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DEFINE(VM_EXEC, VM_EXEC);
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BLANK();
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DEFINE(PAGE_SZ, PAGE_SIZE);
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BLANK();
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DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
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DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
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BLANK();
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DEFINE(PREEMPT_DISABLE_OFFSET, PREEMPT_DISABLE_OFFSET);
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DEFINE(SOFTIRQ_SHIFT, SOFTIRQ_SHIFT);
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DEFINE(IRQ_CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
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BLANK();
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DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task));
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BLANK();
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DEFINE(FTR_OVR_VAL_OFFSET, offsetof(struct arm64_ftr_override, val));
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DEFINE(FTR_OVR_MASK_OFFSET, offsetof(struct arm64_ftr_override, mask));
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BLANK();
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#ifdef CONFIG_KVM
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DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
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DEFINE(VCPU_FAULT_DISR, offsetof(struct kvm_vcpu, arch.fault.disr_el1));
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DEFINE(VCPU_WORKAROUND_FLAGS, offsetof(struct kvm_vcpu, arch.workaround_flags));
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DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2));
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DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_cpu_context, regs));
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DEFINE(CPU_RGSR_EL1, offsetof(struct kvm_cpu_context, sys_regs[RGSR_EL1]));
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DEFINE(CPU_GCR_EL1, offsetof(struct kvm_cpu_context, sys_regs[GCR_EL1]));
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DEFINE(CPU_APIAKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APIAKEYLO_EL1]));
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DEFINE(CPU_APIBKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APIBKEYLO_EL1]));
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DEFINE(CPU_APDAKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APDAKEYLO_EL1]));
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DEFINE(CPU_APDBKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APDBKEYLO_EL1]));
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DEFINE(CPU_APGAKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APGAKEYLO_EL1]));
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DEFINE(HOST_CONTEXT_VCPU, offsetof(struct kvm_cpu_context, __hyp_running_vcpu));
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DEFINE(HOST_DATA_CONTEXT, offsetof(struct kvm_host_data, host_ctxt));
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DEFINE(NVHE_INIT_MAIR_EL2, offsetof(struct kvm_nvhe_init_params, mair_el2));
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DEFINE(NVHE_INIT_TCR_EL2, offsetof(struct kvm_nvhe_init_params, tcr_el2));
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DEFINE(NVHE_INIT_TPIDR_EL2, offsetof(struct kvm_nvhe_init_params, tpidr_el2));
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DEFINE(NVHE_INIT_STACK_HYP_VA, offsetof(struct kvm_nvhe_init_params, stack_hyp_va));
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DEFINE(NVHE_INIT_PGD_PA, offsetof(struct kvm_nvhe_init_params, pgd_pa));
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DEFINE(NVHE_INIT_HCR_EL2, offsetof(struct kvm_nvhe_init_params, hcr_el2));
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DEFINE(NVHE_INIT_VTTBR, offsetof(struct kvm_nvhe_init_params, vttbr));
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DEFINE(NVHE_INIT_VTCR, offsetof(struct kvm_nvhe_init_params, vtcr));
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#endif
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#ifdef CONFIG_CPU_PM
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DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
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DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
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DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
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DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs));
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DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs));
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#endif
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DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
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DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
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DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
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DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
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DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0));
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DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2));
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DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4));
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DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6));
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DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8));
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DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10));
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DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12));
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DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14));
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DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16));
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BLANK();
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DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address));
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DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address));
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DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next));
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DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val));
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BLANK();
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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DEFINE(TRAMP_VALIAS, TRAMP_VALIAS);
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#endif
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#ifdef CONFIG_ARM_SDE_INTERFACE
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DEFINE(SDEI_EVENT_INTREGS, offsetof(struct sdei_registered_event, interrupted_regs));
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DEFINE(SDEI_EVENT_PRIORITY, offsetof(struct sdei_registered_event, priority));
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#endif
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#ifdef CONFIG_ARM64_PTR_AUTH
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DEFINE(PTRAUTH_USER_KEY_APIA, offsetof(struct ptrauth_keys_user, apia));
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#ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
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DEFINE(PTRAUTH_KERNEL_KEY_APIA, offsetof(struct ptrauth_keys_kernel, apia));
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#endif
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BLANK();
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#endif
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return 0;
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}
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