mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-26 20:44:32 +08:00
81ec988981
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
23 lines
329 B
C
23 lines
329 B
C
#ifndef _ASM_CLKDEV_H
|
|
#define _ASM_CLKDEV_H
|
|
|
|
#include <linux/slab.h>
|
|
|
|
struct clk;
|
|
|
|
static inline int __clk_get(struct clk *clk)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
static inline void __clk_put(struct clk *clk)
|
|
{
|
|
}
|
|
|
|
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
|
|
{
|
|
return kzalloc(size, GFP_KERNEL);
|
|
}
|
|
|
|
#endif /* _ASM_CLKDEV_H */
|