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ARCHes with special requirements for evicting THP backing TLB entries can implement this. Otherwise also, it can help optimize TLB flush in THP regime. stock flush_tlb_range() typically has optimization to nuke the entire TLB if flush span is greater than a certain threshhold, which will likely be true for a single huge page. Thus a single thp flush will invalidate the entrire TLB which is not desirable. e.g. see arch/arc: flush_pmd_tlb_range Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Link: http://lkml.kernel.org/r/20151009100816.GC7873@node Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
218 lines
5.7 KiB
C
218 lines
5.7 KiB
C
/*
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* mm/pgtable-generic.c
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*
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* Generic pgtable methods declared in asm-generic/pgtable.h
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*
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* Copyright (C) 2010 Linus Torvalds
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*/
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#include <linux/pagemap.h>
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#include <asm/tlb.h>
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#include <asm-generic/pgtable.h>
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/*
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* If a p?d_bad entry is found while walking page tables, report
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* the error, before resetting entry to p?d_none. Usually (but
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* very seldom) called out from the p?d_none_or_clear_bad macros.
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*/
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void pgd_clear_bad(pgd_t *pgd)
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{
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pgd_ERROR(*pgd);
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pgd_clear(pgd);
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}
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void pud_clear_bad(pud_t *pud)
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{
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pud_ERROR(*pud);
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pud_clear(pud);
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}
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void pmd_clear_bad(pmd_t *pmd)
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{
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pmd_ERROR(*pmd);
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pmd_clear(pmd);
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}
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#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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/*
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* Only sets the access flags (dirty, accessed), as well as write
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* permission. Furthermore, we know it always gets set to a "more
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* permissive" setting, which allows most architectures to optimize
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* this. We return whether the PTE actually changed, which in turn
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* instructs the caller to do things like update__mmu_cache. This
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* used to be done in the caller, but sparc needs minor faults to
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* force that call on sun4c so we changed this macro slightly
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*/
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int ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep,
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pte_t entry, int dirty)
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{
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int changed = !pte_same(*ptep, entry);
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if (changed) {
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set_pte_at(vma->vm_mm, address, ptep, entry);
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flush_tlb_fix_spurious_fault(vma, address);
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}
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return changed;
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}
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#endif
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#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
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int ptep_clear_flush_young(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep)
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{
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int young;
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young = ptep_test_and_clear_young(vma, address, ptep);
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if (young)
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flush_tlb_page(vma, address);
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return young;
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}
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#endif
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#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
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pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep)
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{
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struct mm_struct *mm = (vma)->vm_mm;
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pte_t pte;
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pte = ptep_get_and_clear(mm, address, ptep);
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if (pte_accessible(mm, pte))
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flush_tlb_page(vma, address);
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return pte;
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}
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#endif
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
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/*
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* ARCHes with special requirements for evicting THP backing TLB entries can
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* implement this. Otherwise also, it can help optimize normal TLB flush in
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* THP regime. stock flush_tlb_range() typically has optimization to nuke the
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* entire TLB TLB if flush span is greater than a threshhold, which will
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* likely be true for a single huge page. Thus a single thp flush will
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* invalidate the entire TLB which is not desitable.
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* e.g. see arch/arc: flush_pmd_tlb_range
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*/
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#define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
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#endif
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#ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
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int pmdp_set_access_flags(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp,
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pmd_t entry, int dirty)
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{
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int changed = !pmd_same(*pmdp, entry);
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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if (changed) {
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set_pmd_at(vma->vm_mm, address, pmdp, entry);
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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}
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return changed;
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}
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#endif
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#ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
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int pmdp_clear_flush_young(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp)
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{
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int young;
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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young = pmdp_test_and_clear_young(vma, address, pmdp);
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if (young)
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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return young;
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}
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#endif
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#ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
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pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, unsigned long address,
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pmd_t *pmdp)
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{
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pmd_t pmd;
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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VM_BUG_ON(!pmd_trans_huge(*pmdp));
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pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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return pmd;
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}
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#endif
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#ifndef __HAVE_ARCH_PMDP_SPLITTING_FLUSH
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void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
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pmd_t *pmdp)
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{
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pmd_t pmd = pmd_mksplitting(*pmdp);
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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set_pmd_at(vma->vm_mm, address, pmdp, pmd);
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/* tlb flush only to serialize against gup-fast */
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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}
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#endif
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#ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
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void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable)
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{
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assert_spin_locked(pmd_lockptr(mm, pmdp));
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/* FIFO */
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if (!pmd_huge_pte(mm, pmdp))
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INIT_LIST_HEAD(&pgtable->lru);
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else
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list_add(&pgtable->lru, &pmd_huge_pte(mm, pmdp)->lru);
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pmd_huge_pte(mm, pmdp) = pgtable;
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}
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#endif
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#ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
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/* no "address" argument so destroys page coloring of some arch */
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pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
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{
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pgtable_t pgtable;
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assert_spin_locked(pmd_lockptr(mm, pmdp));
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/* FIFO */
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pgtable = pmd_huge_pte(mm, pmdp);
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if (list_empty(&pgtable->lru))
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pmd_huge_pte(mm, pmdp) = NULL;
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else {
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pmd_huge_pte(mm, pmdp) = list_entry(pgtable->lru.next,
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struct page, lru);
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list_del(&pgtable->lru);
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}
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return pgtable;
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}
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#endif
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#ifndef __HAVE_ARCH_PMDP_INVALIDATE
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void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
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pmd_t *pmdp)
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{
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pmd_t entry = *pmdp;
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set_pmd_at(vma->vm_mm, address, pmdp, pmd_mknotpresent(entry));
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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}
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#endif
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#ifndef pmdp_collapse_flush
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pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
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pmd_t *pmdp)
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{
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/*
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* pmd and hugepage pte format are same. So we could
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* use the same function.
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*/
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pmd_t pmd;
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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VM_BUG_ON(pmd_trans_huge(*pmdp));
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pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
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flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
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return pmd;
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}
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#endif
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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