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c9c256a8b0
'sdhci_remove_host()' and 'sdhci_pltfm_free()' should be used in place of
'mmc_remove_host()' and 'mmc_free_host()'.
This avoids some resource leaks, is more in line with the error handling
path of the probe function, and is more consistent with other drivers.
Fixes: fb8bd90f83
("mmc: sdhci-sprd: Add Spreadtrum's initial host controller")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Orson Zhai <orson.zhai@gmail.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20201217204236.163446-1-christophe.jaillet@wanadoo.fr
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
800 lines
21 KiB
C
800 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Secure Digital Host Controller
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//
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// Copyright (C) 2018 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "sdhci-pltfm.h"
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#include "mmc_hsq.h"
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/* SDHCI_ARGUMENT2 register high 16bit */
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#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
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#define SDHCI_SPRD_REG_32_DLL_CFG 0x200
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#define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
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#define SDHCI_SPRD_DLL_EN BIT(21)
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#define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
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#define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
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#define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
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#define SDHCI_SPRD_REG_32_DLL_DLY 0x204
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#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
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#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
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#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
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#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
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#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
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#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
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#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
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#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
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#define SDHCI_SPRD_REG_DEBOUNCE 0x28C
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#define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
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#define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
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#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
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/* SDHCI_HOST_CONTROL2 */
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#define SDHCI_SPRD_CTRL_HS200 0x0005
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#define SDHCI_SPRD_CTRL_HS400 0x0006
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#define SDHCI_SPRD_CTRL_HS400ES 0x0007
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/*
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* According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
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* reserved, and only used on Spreadtrum's design, the hardware cannot work
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* if this bit is cleared.
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* 1 : normal work
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* 0 : hardware reset
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*/
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#define SDHCI_HW_RESET_CARD BIT(3)
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#define SDHCI_SPRD_MAX_CUR 0xFFFFFF
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#define SDHCI_SPRD_CLK_MAX_DIV 1023
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#define SDHCI_SPRD_CLK_DEF_RATE 26000000
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#define SDHCI_SPRD_PHY_DLL_CLK 52000000
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struct sdhci_sprd_host {
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u32 version;
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struct clk *clk_sdio;
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struct clk *clk_enable;
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struct clk *clk_2x_enable;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_uhs;
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struct pinctrl_state *pins_default;
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u32 base_rate;
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int flags; /* backup of host attribute */
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u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
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};
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struct sdhci_sprd_phy_cfg {
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const char *property;
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u8 timing;
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};
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static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
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{ "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
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{ "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
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{ "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
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{ "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
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{ "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
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{ "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
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{ "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
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{ "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
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{ "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
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};
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#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
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static void sdhci_sprd_init_config(struct sdhci_host *host)
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{
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u16 val;
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/* set dll backup mode */
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val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
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val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
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sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
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}
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static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
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{
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if (unlikely(reg == SDHCI_MAX_CURRENT))
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return SDHCI_SPRD_MAX_CUR;
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return readl_relaxed(host->ioaddr + reg);
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}
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static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
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{
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/* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
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if (unlikely(reg == SDHCI_MAX_CURRENT))
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return;
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if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
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val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
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writel_relaxed(val, host->ioaddr + reg);
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}
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static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
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{
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/* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
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if (unlikely(reg == SDHCI_BLOCK_COUNT))
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return;
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writew_relaxed(val, host->ioaddr + reg);
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}
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static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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/*
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* Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
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* standard specification, sdhci_reset() write this register directly
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* without checking other reserved bits, that will clear BIT(3) which
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* is defined as hardware reset on Spreadtrum's platform and clearing
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* it by mistake will lead the card not work. So here we need to work
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* around it.
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*/
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if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
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if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
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val |= SDHCI_HW_RESET_CARD;
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}
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writeb_relaxed(val, host->ioaddr + reg);
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}
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static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
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{
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u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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ctrl &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
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}
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static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
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{
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u16 ctrl;
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ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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ctrl |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
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}
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static inline void
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sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
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{
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u32 dll_dly_offset;
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dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
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if (en)
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dll_dly_offset |= mask;
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else
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dll_dly_offset &= ~mask;
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sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
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}
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static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
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{
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u32 div;
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/* select 2x clock source */
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if (base_clk <= clk * 2)
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return 0;
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div = (u32) (base_clk / (clk * 2));
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if ((base_clk / div) > (clk * 2))
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div++;
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if (div > SDHCI_SPRD_CLK_MAX_DIV)
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div = SDHCI_SPRD_CLK_MAX_DIV;
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if (div % 2)
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div = (div + 1) / 2;
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else
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div = div / 2;
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return div;
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}
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static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
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unsigned int clk)
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{
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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u32 div, val, mask;
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
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div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
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sdhci_enable_clk(host, div);
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/* enable auto gate sdhc_enable_auto_gate */
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val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
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mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
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SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
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if (mask != (val & mask)) {
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val |= mask;
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sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
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}
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}
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static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
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{
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u32 tmp;
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tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
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tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
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sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
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/* wait 1ms */
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usleep_range(1000, 1250);
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tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
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tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
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SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
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sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
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/* wait 1ms */
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usleep_range(1000, 1250);
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tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
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tmp |= SDHCI_SPRD_DLL_EN;
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sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
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/* wait 1ms */
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usleep_range(1000, 1250);
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}
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static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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bool en = false, clk_changed = false;
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if (clock == 0) {
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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} else if (clock != host->clock) {
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sdhci_sprd_sd_clk_off(host);
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_sdhci_sprd_set_clock(host, clock);
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if (clock <= 400000)
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en = true;
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sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
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SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
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clk_changed = true;
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} else {
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_sdhci_sprd_set_clock(host, clock);
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}
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/*
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* According to the Spreadtrum SD host specification, when we changed
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* the clock to be more than 52M, we should enable the PHY DLL which
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* is used to track the clock frequency to make the clock work more
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* stable. Otherwise deviation may occur of the higher clock.
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*/
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if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
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sdhci_sprd_enable_phy_dll(host);
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}
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static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
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}
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static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
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{
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return 400000;
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}
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static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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struct mmc_host *mmc = host->mmc;
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u32 *p = sprd_host->phy_delay;
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u16 ctrl_2;
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if (timing == host->timing)
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return;
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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switch (timing) {
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case MMC_TIMING_UHS_SDR12:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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break;
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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break;
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case MMC_TIMING_UHS_SDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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break;
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case MMC_TIMING_UHS_SDR104:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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break;
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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break;
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case MMC_TIMING_MMC_HS200:
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ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
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break;
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case MMC_TIMING_MMC_HS400:
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ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
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break;
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default:
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break;
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}
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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if (!mmc->ios.enhanced_strobe)
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sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
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}
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static void sdhci_sprd_hw_reset(struct sdhci_host *host)
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{
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int val;
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/*
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* Note: don't use sdhci_writeb() API here since it is redirected to
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* sdhci_sprd_writeb() in which we have a workaround for
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* SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
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* not be cleared.
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*/
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val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
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val &= ~SDHCI_HW_RESET_CARD;
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writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
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/* wait for 10 us */
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usleep_range(10, 20);
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val |= SDHCI_HW_RESET_CARD;
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writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
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usleep_range(300, 500);
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}
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static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
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{
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/* The Spredtrum controller actual maximum timeout count is 1 << 31 */
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return 1 << 31;
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}
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static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
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{
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return 0;
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}
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static void sdhci_sprd_request_done(struct sdhci_host *host,
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struct mmc_request *mrq)
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{
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/* Validate if the request was from software queue firstly. */
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if (mmc_hsq_finalize_request(host->mmc, mrq))
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return;
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mmc_request_done(host->mmc, mrq);
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}
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static struct sdhci_ops sdhci_sprd_ops = {
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.read_l = sdhci_sprd_readl,
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.write_l = sdhci_sprd_writel,
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.write_b = sdhci_sprd_writeb,
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.set_clock = sdhci_sprd_set_clock,
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.get_max_clock = sdhci_sprd_get_max_clock,
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.get_min_clock = sdhci_sprd_get_min_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
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.hw_reset = sdhci_sprd_hw_reset,
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.get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
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.get_ro = sdhci_sprd_get_ro,
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.request_done = sdhci_sprd_request_done,
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};
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static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
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struct mmc_request *mrq)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
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/*
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* From version 4.10 onward, ARGUMENT2 register is also as 32-bit
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* block count register which doesn't support stuff bits of
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* CMD23 argument on Spreadtrum's sd host controller.
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*/
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if (host->version >= SDHCI_SPEC_410 &&
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mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
|
|
(host->flags & SDHCI_AUTO_CMD23))
|
|
host->flags &= ~SDHCI_AUTO_CMD23;
|
|
}
|
|
|
|
static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
sdhci_sprd_check_auto_cmd23(mmc, mrq);
|
|
|
|
sdhci_request(mmc, mrq);
|
|
}
|
|
|
|
static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
|
|
struct mmc_request *mrq)
|
|
{
|
|
sdhci_sprd_check_auto_cmd23(mmc, mrq);
|
|
|
|
return sdhci_request_atomic(mmc, mrq);
|
|
}
|
|
|
|
static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
|
|
int ret;
|
|
|
|
if (!IS_ERR(mmc->supply.vqmmc)) {
|
|
ret = mmc_regulator_set_vqmmc(mmc, ios);
|
|
if (ret < 0) {
|
|
pr_err("%s: Switching signalling voltage failed\n",
|
|
mmc_hostname(mmc));
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (IS_ERR(sprd_host->pinctrl))
|
|
return 0;
|
|
|
|
switch (ios->signal_voltage) {
|
|
case MMC_SIGNAL_VOLTAGE_180:
|
|
ret = pinctrl_select_state(sprd_host->pinctrl,
|
|
sprd_host->pins_uhs);
|
|
if (ret) {
|
|
pr_err("%s: failed to select uhs pin state\n",
|
|
mmc_hostname(mmc));
|
|
return ret;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fallthrough;
|
|
case MMC_SIGNAL_VOLTAGE_330:
|
|
ret = pinctrl_select_state(sprd_host->pinctrl,
|
|
sprd_host->pins_default);
|
|
if (ret) {
|
|
pr_err("%s: failed to select default pin state\n",
|
|
mmc_hostname(mmc));
|
|
return ret;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* Wait for 300 ~ 500 us for pin state stable */
|
|
usleep_range(300, 500);
|
|
sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
|
|
struct mmc_ios *ios)
|
|
{
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
|
|
u32 *p = sprd_host->phy_delay;
|
|
u16 ctrl_2;
|
|
|
|
if (!ios->enhanced_strobe)
|
|
return;
|
|
|
|
sdhci_sprd_sd_clk_off(host);
|
|
|
|
/* Set HS400 enhanced strobe mode */
|
|
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
|
|
ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
|
|
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
|
|
|
|
sdhci_sprd_sd_clk_on(host);
|
|
|
|
/* Set the PHY DLL delay value for HS400 enhanced strobe mode */
|
|
sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
|
|
SDHCI_SPRD_REG_32_DLL_DLY);
|
|
}
|
|
|
|
static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
|
|
struct device_node *np)
|
|
{
|
|
u32 *p = sprd_host->phy_delay;
|
|
int ret, i, index;
|
|
u32 val[4];
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
|
|
ret = of_property_read_u32_array(np,
|
|
sdhci_sprd_phy_cfgs[i].property, val, 4);
|
|
if (ret)
|
|
continue;
|
|
|
|
index = sdhci_sprd_phy_cfgs[i].timing;
|
|
p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
|
|
}
|
|
}
|
|
|
|
static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
|
SDHCI_QUIRK_MISSING_CAPS,
|
|
.quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
|
|
SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
|
|
SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
.ops = &sdhci_sprd_ops,
|
|
};
|
|
|
|
static int sdhci_sprd_probe(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host;
|
|
struct sdhci_sprd_host *sprd_host;
|
|
struct mmc_hsq *hsq;
|
|
struct clk *clk;
|
|
int ret = 0;
|
|
|
|
host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
host->dma_mask = DMA_BIT_MASK(64);
|
|
pdev->dev.dma_mask = &host->dma_mask;
|
|
host->mmc_host_ops.request = sdhci_sprd_request;
|
|
host->mmc_host_ops.hs400_enhanced_strobe =
|
|
sdhci_sprd_hs400_enhanced_strobe;
|
|
/*
|
|
* We can not use the standard ops to change and detect the voltage
|
|
* signal for Spreadtrum SD host controller, since our voltage regulator
|
|
* for I/O is fixed in hardware, that means we do not need control
|
|
* the standard SD host controller to change the I/O voltage.
|
|
*/
|
|
host->mmc_host_ops.start_signal_voltage_switch =
|
|
sdhci_sprd_voltage_switch;
|
|
|
|
host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
|
|
MMC_CAP_WAIT_WHILE_BUSY;
|
|
|
|
ret = mmc_of_parse(host->mmc);
|
|
if (ret)
|
|
goto pltfm_free;
|
|
|
|
if (!mmc_card_is_removable(host->mmc))
|
|
host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
|
|
else
|
|
host->always_defer_done = true;
|
|
|
|
sprd_host = TO_SPRD_HOST(host);
|
|
sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
|
|
|
|
sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
|
|
if (!IS_ERR(sprd_host->pinctrl)) {
|
|
sprd_host->pins_uhs =
|
|
pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
|
|
if (IS_ERR(sprd_host->pins_uhs)) {
|
|
ret = PTR_ERR(sprd_host->pins_uhs);
|
|
goto pltfm_free;
|
|
}
|
|
|
|
sprd_host->pins_default =
|
|
pinctrl_lookup_state(sprd_host->pinctrl, "default");
|
|
if (IS_ERR(sprd_host->pins_default)) {
|
|
ret = PTR_ERR(sprd_host->pins_default);
|
|
goto pltfm_free;
|
|
}
|
|
}
|
|
|
|
clk = devm_clk_get(&pdev->dev, "sdio");
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto pltfm_free;
|
|
}
|
|
sprd_host->clk_sdio = clk;
|
|
sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
|
|
if (!sprd_host->base_rate)
|
|
sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
|
|
|
|
clk = devm_clk_get(&pdev->dev, "enable");
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto pltfm_free;
|
|
}
|
|
sprd_host->clk_enable = clk;
|
|
|
|
clk = devm_clk_get(&pdev->dev, "2x_enable");
|
|
if (!IS_ERR(clk))
|
|
sprd_host->clk_2x_enable = clk;
|
|
|
|
ret = clk_prepare_enable(sprd_host->clk_sdio);
|
|
if (ret)
|
|
goto pltfm_free;
|
|
|
|
ret = clk_prepare_enable(sprd_host->clk_enable);
|
|
if (ret)
|
|
goto clk_disable;
|
|
|
|
ret = clk_prepare_enable(sprd_host->clk_2x_enable);
|
|
if (ret)
|
|
goto clk_disable2;
|
|
|
|
sdhci_sprd_init_config(host);
|
|
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
|
|
sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
|
|
SDHCI_VENDOR_VER_SHIFT);
|
|
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_suspend_ignore_children(&pdev->dev, 1);
|
|
|
|
sdhci_enable_v4_mode(host);
|
|
|
|
/*
|
|
* Supply the existing CAPS, but clear the UHS-I modes. This
|
|
* will allow these modes to be specified only by device
|
|
* tree properties through mmc_of_parse().
|
|
*/
|
|
host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
|
|
host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
|
|
host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
|
|
SDHCI_SUPPORT_DDR50);
|
|
|
|
ret = sdhci_setup_host(host);
|
|
if (ret)
|
|
goto pm_runtime_disable;
|
|
|
|
sprd_host->flags = host->flags;
|
|
|
|
hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
|
|
if (!hsq) {
|
|
ret = -ENOMEM;
|
|
goto err_cleanup_host;
|
|
}
|
|
|
|
ret = mmc_hsq_init(hsq, host->mmc);
|
|
if (ret)
|
|
goto err_cleanup_host;
|
|
|
|
ret = __sdhci_add_host(host);
|
|
if (ret)
|
|
goto err_cleanup_host;
|
|
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
err_cleanup_host:
|
|
sdhci_cleanup_host(host);
|
|
|
|
pm_runtime_disable:
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
|
|
clk_disable_unprepare(sprd_host->clk_2x_enable);
|
|
|
|
clk_disable2:
|
|
clk_disable_unprepare(sprd_host->clk_enable);
|
|
|
|
clk_disable:
|
|
clk_disable_unprepare(sprd_host->clk_sdio);
|
|
|
|
pltfm_free:
|
|
sdhci_pltfm_free(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_sprd_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
|
|
|
|
sdhci_remove_host(host, 0);
|
|
|
|
clk_disable_unprepare(sprd_host->clk_sdio);
|
|
clk_disable_unprepare(sprd_host->clk_enable);
|
|
clk_disable_unprepare(sprd_host->clk_2x_enable);
|
|
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sdhci_sprd_of_match[] = {
|
|
{ .compatible = "sprd,sdhci-r11", },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sdhci_sprd_runtime_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
|
|
|
|
mmc_hsq_suspend(host->mmc);
|
|
sdhci_runtime_suspend_host(host);
|
|
|
|
clk_disable_unprepare(sprd_host->clk_sdio);
|
|
clk_disable_unprepare(sprd_host->clk_enable);
|
|
clk_disable_unprepare(sprd_host->clk_2x_enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sdhci_sprd_runtime_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(sprd_host->clk_2x_enable);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(sprd_host->clk_enable);
|
|
if (ret)
|
|
goto clk_2x_disable;
|
|
|
|
ret = clk_prepare_enable(sprd_host->clk_sdio);
|
|
if (ret)
|
|
goto clk_disable;
|
|
|
|
sdhci_runtime_resume_host(host, 1);
|
|
mmc_hsq_resume(host->mmc);
|
|
|
|
return 0;
|
|
|
|
clk_disable:
|
|
clk_disable_unprepare(sprd_host->clk_enable);
|
|
|
|
clk_2x_disable:
|
|
clk_disable_unprepare(sprd_host->clk_2x_enable);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops sdhci_sprd_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
|
|
sdhci_sprd_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver sdhci_sprd_driver = {
|
|
.probe = sdhci_sprd_probe,
|
|
.remove = sdhci_sprd_remove,
|
|
.driver = {
|
|
.name = "sdhci_sprd_r11",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.of_match_table = sdhci_sprd_of_match,
|
|
.pm = &sdhci_sprd_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(sdhci_sprd_driver);
|
|
|
|
MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:sdhci-sprd-r11");
|