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[ Upstream commit0734f8311c] CN9130 has a built-in CP115 which has 2 GPIO controllers, but unlike in Armada 7k and 8k both are left disabled by the SoC DTSI. This first of all makes no sense as they are always present due to being SoC built-in and its an issue as boards like CN9130-CRB use the CPO GPIO2 pins for regulators and SD card support without enabling them first. So, enable both of them like Armada 7k and 8k do. Fixes:6b8970bd8d("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
53 lines
1.0 KiB
Plaintext
53 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* Device tree for the CN9130 SoC.
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*/
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#include "armada-ap807-quad.dtsi"
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/ {
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model = "Marvell Armada CN9130 SoC";
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compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
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"marvell,armada-ap807";
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aliases {
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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};
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};
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/*
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* Instantiate the internal CP115
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
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0xe0000000 + ((iface - 1) * 0x1000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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#define CP11X_PCIE2_BASE f2640000
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#include "armada-cp115.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp0_gpio1 {
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status = "okay";
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};
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&cp0_gpio2 {
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status = "okay";
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};
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