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The CN913x DB with topology B is similar to a regular setup (A) boards, but uses NAND flash as a boot device, while topology A boards are booting from SPI flash. Since NAND and SPI on CN913x DB boards share some wires, they cannot be activated simultaneously. The DTS files for setup "B" are based on setup "A", in which the CP0 NAND controller enabled and CP0 SPI1 disabled. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
23 lines
495 B
Plaintext
23 lines
495 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* Device tree for the CN9130-DB board.
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*/
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#include "cn9130-db.dtsi"
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/ {
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model = "Marvell Armada CN9130-DB setup A";
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};
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/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
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* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
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* simultaneously. When SPI controller is enabled, NAND should be disabled.
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*/
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&cp0_spi1 {
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status = "okay";
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};
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