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f7857bf374
There are six new SoCs added this time. Apple M1 and Nuvoton WPCM450
have separate branches because they are new SoC families that require
changes outside of device tree files. The other four are variations of
already supported chips and get merged through this branch:
- STMicroelectronics STM32H750 is one of many variants of STM32
microcontrollers based on the Cortex-M7 core. This is particularly
notable since we rarely add support for new MMU-less chips
these days. In this case, the board that gets added along with
the platform is not a SoC reference platform but the "Art Pi"
(https://art-pi.gitee.io/website/) machine that was originally design
for the RT-Thread RTOS.
- NXP i.MX8QuadMax is a variant of the growing i.MX8 embedded/industrial
SoC family, using two Cortex-A72 and four Cortex-A53 cores. It
gets added along with its reference board, the "NXP i.MX8QuadMax
Multisensory Enablement Kit".
- Qualcomm SC7280 is a Laptop SoC following the SC7180 (Snapdragon 7c)
that is used in some Chromebooks and Windows laptops. Only a reference
board is added for the moment.
- TI AM64x Sita4ra is a new version of the K3 SoC family for industrial
control, motor control, remote IO, IoT gateway etc., similar to the
older AM65x family. Two reference machines are added alongside.
Among the newly added machines, there is a very clear skew towards 64-bit
machines now, with 12 32-bit machines compared to 23 64-bit machines. The
full list sorted by SoC is:
- ASpeed AST2500 BMC: ASRock E3C246D4I Xeon server board
- Allwinner A10: Topwise A721 Tablet
- Amlogic GXL: MeCool KII TV box
- Amlogic GXM: Mecool KIII, Minix Neo U9-H TV boxes
- Broadcom BCM4908: TP-Link Archer C2300 V1 router
- MStar SSD202D: M5Stack UnitV2 camera
- Marvell Armada 38x: ATL-x530 ethernet switch
- Mediatek MT8183 Chromebooks: Lenovo 10e, Acer Spin 311,
Asus Flip CM3, Asus Detachable CM3
- Mediatek MT8516/MT8183: OLogic Pumpkin Board
- NXP i.MX7: reMarkable Tablet
- NXP i.MX8M: Kontron pitx-imx8m, Engicam i.Core MX8M Mini
- Nuvoton NPCM730: Quanta GBS BMC
- Qualcomm X55: Telit FN980 TLB SoM, Thundercomm TurboX T55 SoM
- Qualcomm MSM8998: OnePlus 5/5T phones
- Qualcomm SM8350: Snapdragon 888 Mobile Hardware Development Kit
- Rockchip RK3399: NanoPi R4S board
- STM32MP1: Engicam MicroGEA STM32MP1 MicroDev 2.0 and SOM,
EDIMM2.2 Starter Kit, Carrier, SOM
- TI AM65: Siemens SIMATIC IOT2050 gateway
There is notable work going into extending already supported machines
and SoCs:
- ASpeed AST2500
- Allwinner A23, A83t, A31, A64, H6
- Amlogic G12B
- Broadcom BCM4908
- Marvell Armada 7K/8K/CN91xx
- Mediatek MT6589, MT7622, MT8173, MT8183, MT8195
- NXP i.MX8Q, i.MX8MM, i.MX8MP
- Qualcomm MSM8916, SC7180, SDM845, SDX55, SM8350
- Renesas R-Car M3, V3U
- Rockchip RK3328, RK3399
- STEricsson U8500
- STMicroelectronics STM32MP141
- Samsung Exynos 4412
- TI K3-AM65, K3-J7200
- TI OMAP3
Among the treewide cleanups and bug fixes, two parts stand out:
- There are a number of cleanups for issues pointed out by 'make
dtbs_check' this time, and I expect more to come in the future as we
increasingly check for regressions.
- After a change to the MMC subsystem that can lead to unpredictable
device numbers, several platforms add 'aliases' properties for these
to give each MMC controller a fixed number.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"There are six new SoCs added this time.
Apple M1 and Nuvoton WPCM450 have separate branches because they are
new SoC families that require changes outside of device tree files.
The other four are variations of already supported chips and get
merged through this branch:
- STMicroelectronics STM32H750 is one of many variants of STM32
microcontrollers based on the Cortex-M7 core.
This is particularly notable since we rarely add support for new
MMU-less chips these days. In this case, the board that gets added
along with the platform is not a SoC reference platform but the
"Art Pi" (https://art-pi.gitee.io/website/) machine that was
originally design for the RT-Thread RTOS.
- NXP i.MX8QuadMax is a variant of the growing i.MX8
embedded/industrial SoC family, using two Cortex-A72 and four
Cortex-A53 cores.
It gets added along with its reference board, the "NXP i.MX8QuadMax
Multisensory Enablement Kit".
- Qualcomm SC7280 is a Laptop SoC following the SC7180 (Snapdragon
7c) that is used in some Chromebooks and Windows laptops.
Only a reference board is added for the moment.
- TI AM64x Sita4ra is a new version of the K3 SoC family for
industrial control, motor control, remote IO, IoT gateway etc.,
similar to the older AM65x family.
Two reference machines are added alongside.
Among the newly added machines, there is a very clear skew towards
64-bit machines now, with 12 32-bit machines compared to 23 64-bit
machines. The full list sorted by SoC is:
- ASpeed AST2500 BMC: ASRock E3C246D4I Xeon server board
- Allwinner A10: Topwise A721 Tablet
- Amlogic GXL: MeCool KII TV box
- Amlogic GXM: Mecool KIII, Minix Neo U9-H TV boxes
- Broadcom BCM4908: TP-Link Archer C2300 V1 router
- MStar SSD202D: M5Stack UnitV2 camera
- Marvell Armada 38x: ATL-x530 ethernet switch
- Mediatek MT8183 Chromebooks: Lenovo 10e, Acer Spin 311, Asus Flip
CM3, Asus Detachable CM3
- Mediatek MT8516/MT8183: OLogic Pumpkin Board
- NXP i.MX7: reMarkable Tablet
- NXP i.MX8M: Kontron pitx-imx8m, Engicam i.Core MX8M Mini
- Nuvoton NPCM730: Quanta GBS BMC
- Qualcomm X55: Telit FN980 TLB SoM, Thundercomm TurboX T55 SoM
- Qualcomm MSM8998: OnePlus 5/5T phones
- Qualcomm SM8350: Snapdragon 888 Mobile Hardware Development Kit
- Rockchip RK3399: NanoPi R4S board
- STM32MP1: Engicam MicroGEA STM32MP1 MicroDev 2.0 and SOM, EDIMM2.2
Starter Kit, Carrier, SOM
- TI AM65: Siemens SIMATIC IOT2050 gateway
There is notable work going into extending already supported machines
and SoCs:
- ASpeed AST2500
- Allwinner A23, A83t, A31, A64, H6
- Amlogic G12B
- Broadcom BCM4908
- Marvell Armada 7K/8K/CN91xx
- Mediatek MT6589, MT7622, MT8173, MT8183, MT8195
- NXP i.MX8Q, i.MX8MM, i.MX8MP
- Qualcomm MSM8916, SC7180, SDM845, SDX55, SM8350
- Renesas R-Car M3, V3U
- Rockchip RK3328, RK3399
- STEricsson U8500
- STMicroelectronics STM32MP141
- Samsung Exynos 4412
- TI K3-AM65, K3-J7200
- TI OMAP3
Among the treewide cleanups and bug fixes, two parts stand out:
- There are a number of cleanups for issues pointed out by 'make
dtbs_check' this time, and I expect more to come in the future as
we increasingly check for regressions.
- After a change to the MMC subsystem that can lead to unpredictable
device numbers, several platforms add 'aliases' properties for
these to give each MMC controller a fixed number"
* tag 'arm-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (516 commits)
dt-bindings: mali-bifrost: add dma-coherent
arm64: dts: amlogic: misc DT schema fixups
arm64: dts: qcom: sc7180: Update iommu property for simultaneous playback
arm64: dts: qcom: sc7180: pompom: Add "dmic_clk_en" + sound model
arm64: dts: qcom: sc7180: coachz: Add "dmic_clk_en"
ARM: dts: mstar: Add a dts for M5Stack UnitV2
dt-bindings: arm: mstar: Add compatible for M5Stack UnitV2
dt-bindings: vendor-prefixes: Add vendor prefix for M5Stack
arm64: dts: mt8183: fix dtbs_check warning
arm64: dts: mt8183-pumpkin: fix dtbs_check warning
ARM: dts: aspeed: tiogapass: add hotplug controller
ARM: dts: aspeed: amd-ethanolx: Enable all used I2C busses
ARM: dts: aspeed: Rainier: Update to pass 2 hardware
ARM: dts: aspeed: Rainier 1S4U: Fix fan nodes
ARM: dts: aspeed: Rainier: Fix humidity sensor bus address
ARM: dts: aspeed: Rainier: Fix PCA9552 on bus 8
ARM: dts: qcom: sdx55: add IPA information
ARM: dts: qcom: sdx55: Add basic devicetree support for Thundercomm T55
dt-bindings: arm: qcom: Add binding for Thundercomm T55 kit
ARM: dts: qcom: sdx55: Add basic devicetree support for Telit FN980 TLB
...
598 lines
16 KiB
Plaintext
598 lines
16 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada CP11x.
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*/
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#include <dt-bindings/interrupt-controller/mvebu-icu.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "armada-common.dtsi"
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#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
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/ {
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/*
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* The contents of the node are defined below, in order to
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* save one indentation level
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*/
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CP11X_NAME: CP11X_NAME { };
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/*
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* CPs only have one sensor in the thermal IC.
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*
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* The cooling maps are empty as there are no cooling devices.
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*/
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thermal-zones {
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CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
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polling-delay-passive = <0>; /* Interrupt driven */
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polling-delay = <0>; /* Interrupt driven */
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thermal-sensors = <&CP11X_LABEL(thermal) 0>;
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trips {
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CP11X_LABEL(crit): crit {
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temperature = <100000>; /* mC degrees */
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hysteresis = <2000>; /* mC degrees */
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type = "critical";
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};
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};
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cooling-maps { };
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};
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};
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};
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&CP11X_NAME {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
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ranges;
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config-space@CP11X_BASE {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
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CP11X_LABEL(ethernet): ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
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clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
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<&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
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<&CP11X_LABEL(clk) 1 18>;
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clock-names = "pp_clk", "gop_clk",
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"mg_clk", "mg_core_clk", "axi_clk";
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marvell,system-controller = <&CP11X_LABEL(syscon0)>;
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status = "disabled";
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dma-coherent;
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CP11X_LABEL(eth0): eth0 {
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interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
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<43 IRQ_TYPE_LEVEL_HIGH>,
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<47 IRQ_TYPE_LEVEL_HIGH>,
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<51 IRQ_TYPE_LEVEL_HIGH>,
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<55 IRQ_TYPE_LEVEL_HIGH>,
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<59 IRQ_TYPE_LEVEL_HIGH>,
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<63 IRQ_TYPE_LEVEL_HIGH>,
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<67 IRQ_TYPE_LEVEL_HIGH>,
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<71 IRQ_TYPE_LEVEL_HIGH>,
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<129 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hif0", "hif1", "hif2",
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"hif3", "hif4", "hif5", "hif6", "hif7",
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"hif8", "link";
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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CP11X_LABEL(eth1): eth1 {
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
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<44 IRQ_TYPE_LEVEL_HIGH>,
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<48 IRQ_TYPE_LEVEL_HIGH>,
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<52 IRQ_TYPE_LEVEL_HIGH>,
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<56 IRQ_TYPE_LEVEL_HIGH>,
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<60 IRQ_TYPE_LEVEL_HIGH>,
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<64 IRQ_TYPE_LEVEL_HIGH>,
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<68 IRQ_TYPE_LEVEL_HIGH>,
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<72 IRQ_TYPE_LEVEL_HIGH>,
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<128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hif0", "hif1", "hif2",
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"hif3", "hif4", "hif5", "hif6", "hif7",
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"hif8", "link";
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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CP11X_LABEL(eth2): eth2 {
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
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<45 IRQ_TYPE_LEVEL_HIGH>,
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<49 IRQ_TYPE_LEVEL_HIGH>,
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<53 IRQ_TYPE_LEVEL_HIGH>,
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<57 IRQ_TYPE_LEVEL_HIGH>,
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<61 IRQ_TYPE_LEVEL_HIGH>,
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<65 IRQ_TYPE_LEVEL_HIGH>,
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<69 IRQ_TYPE_LEVEL_HIGH>,
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<73 IRQ_TYPE_LEVEL_HIGH>,
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<127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hif0", "hif1", "hif2",
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"hif3", "hif4", "hif5", "hif6", "hif7",
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"hif8", "link";
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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CP11X_LABEL(comphy): phy@120000 {
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compatible = "marvell,comphy-cp110";
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reg = <0x120000 0x6000>;
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marvell,system-controller = <&CP11X_LABEL(syscon0)>;
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clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
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<&CP11X_LABEL(clk) 1 18>;
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clock-names = "mg_clk", "mg_core_clk", "axi_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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CP11X_LABEL(comphy0): phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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CP11X_LABEL(comphy1): phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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CP11X_LABEL(comphy2): phy@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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CP11X_LABEL(comphy3): phy@3 {
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reg = <3>;
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#phy-cells = <1>;
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};
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CP11X_LABEL(comphy4): phy@4 {
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reg = <4>;
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#phy-cells = <1>;
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};
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CP11X_LABEL(comphy5): phy@5 {
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reg = <5>;
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#phy-cells = <1>;
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};
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};
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CP11X_LABEL(mdio): mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
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<&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
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status = "disabled";
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};
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CP11X_LABEL(xmdio): mdio@12a600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,xmdio";
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reg = <0x12a600 0x10>;
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clocks = <&CP11X_LABEL(clk) 1 5>,
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<&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
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status = "disabled";
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};
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CP11X_LABEL(icu): interrupt-controller@1e0000 {
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compatible = "marvell,cp110-icu";
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reg = <0x1e0000 0x440>;
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#address-cells = <1>;
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#size-cells = <1>;
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CP11X_LABEL(icu_nsr): interrupt-controller@10 {
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compatible = "marvell,cp110-icu-nsr";
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reg = <0x10 0x20>;
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#interrupt-cells = <2>;
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interrupt-controller;
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msi-parent = <&gicp>;
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};
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CP11X_LABEL(icu_sei): interrupt-controller@50 {
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compatible = "marvell,cp110-icu-sei";
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reg = <0x50 0x10>;
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#interrupt-cells = <2>;
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interrupt-controller;
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msi-parent = <&sei>;
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};
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};
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CP11X_LABEL(rtc): rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
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};
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CP11X_LABEL(syscon0): system-controller@440000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x440000 0x2000>;
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CP11X_LABEL(clk): clock {
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compatible = "marvell,cp110-clock";
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#clock-cells = <2>;
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};
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CP11X_LABEL(gpio1): gpio@100 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x100>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
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marvell,pwm-offset = <0x1f0>;
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#pwm-cells = <2>;
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interrupt-controller;
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interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
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<85 IRQ_TYPE_LEVEL_HIGH>,
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<84 IRQ_TYPE_LEVEL_HIGH>,
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<83 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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clock-names = "core", "axi";
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clocks = <&CP11X_LABEL(clk) 1 21>,
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<&CP11X_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP11X_LABEL(gpio2): gpio@140 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x140>;
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ngpios = <31>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
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marvell,pwm-offset = <0x1f0>;
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#pwm-cells = <2>;
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interrupt-controller;
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interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
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<81 IRQ_TYPE_LEVEL_HIGH>,
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<80 IRQ_TYPE_LEVEL_HIGH>,
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<79 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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clock-names = "core", "axi";
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clocks = <&CP11X_LABEL(clk) 1 21>,
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<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(syscon1): system-controller@400000 {
|
|
compatible = "syscon", "simple-mfd";
|
|
reg = <0x400000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
CP11X_LABEL(thermal): thermal-sensor@70 {
|
|
compatible = "marvell,armada-cp110-thermal";
|
|
reg = <0x70 0x10>;
|
|
interrupts-extended =
|
|
<&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(utmi): utmi@580000 {
|
|
compatible = "marvell,cp110-utmi-phy";
|
|
reg = <0x580000 0x2000>;
|
|
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
CP11X_LABEL(utmi0): usb-phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
CP11X_LABEL(utmi1): usb-phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(usb3_0): usb@500000 {
|
|
compatible = "marvell,armada-8k-xhci",
|
|
"generic-xhci";
|
|
reg = <0x500000 0x4000>;
|
|
dma-coherent;
|
|
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 22>,
|
|
<&CP11X_LABEL(clk) 1 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(usb3_1): usb@510000 {
|
|
compatible = "marvell,armada-8k-xhci",
|
|
"generic-xhci";
|
|
reg = <0x510000 0x4000>;
|
|
dma-coherent;
|
|
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 23>,
|
|
<&CP11X_LABEL(clk) 1 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(sata0): sata@540000 {
|
|
compatible = "marvell,armada-8k-ahci",
|
|
"generic-ahci";
|
|
reg = <0x540000 0x30000>;
|
|
dma-coherent;
|
|
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&CP11X_LABEL(clk) 1 15>,
|
|
<&CP11X_LABEL(clk) 1 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
sata-port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
sata-port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(xor0): xor@6a0000 {
|
|
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
|
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 8>,
|
|
<&CP11X_LABEL(clk) 1 14>;
|
|
};
|
|
|
|
CP11X_LABEL(xor1): xor@6c0000 {
|
|
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
|
reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 7>,
|
|
<&CP11X_LABEL(clk) 1 14>;
|
|
};
|
|
|
|
CP11X_LABEL(spi0): spi@700600 {
|
|
compatible = "marvell,armada-380-spi";
|
|
reg = <0x700600 0x50>;
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(spi1): spi@700680 {
|
|
compatible = "marvell,armada-380-spi";
|
|
reg = <0x700680 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(i2c0): i2c@701000 {
|
|
compatible = "marvell,mv78230-i2c";
|
|
reg = <0x701000 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(i2c1): i2c@701100 {
|
|
compatible = "marvell,mv78230-i2c";
|
|
reg = <0x701100 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart0): serial@702000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702000 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart1): serial@702100 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702100 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart2): serial@702200 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart3): serial@702300 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(nand_controller): nand@720000 {
|
|
/*
|
|
* Due to the limitation of the pins available
|
|
* this controller is only usable on the CPM
|
|
* for A7K and on the CPS for A8K.
|
|
*/
|
|
compatible = "marvell,armada-8k-nand-controller",
|
|
"marvell,armada370-nand-controller";
|
|
reg = <0x720000 0x54>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 2>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(trng): trng@760000 {
|
|
compatible = "marvell,armada-8k-rng",
|
|
"inside-secure,safexcel-eip76";
|
|
reg = <0x760000 0x7d>;
|
|
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 25>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "okay";
|
|
};
|
|
|
|
CP11X_LABEL(sdhci0): sdhci@780000 {
|
|
compatible = "marvell,armada-cp110-sdhci";
|
|
reg = <0x780000 0x300>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
|
|
dma-coherent;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(crypto): crypto@800000 {
|
|
compatible = "inside-secure,safexcel-eip197b";
|
|
reg = <0x800000 0x200000>;
|
|
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<92 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mem", "ring0", "ring1",
|
|
"ring2", "ring3", "eip";
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 26>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
|
|
<0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
/* non-prefetchable memory */
|
|
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
|
|
<0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
/* non-prefetchable memory */
|
|
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
|
|
<0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
/* non-prefetchable memory */
|
|
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
};
|