linux/arch/riscv/include
Sergey Matyukevich e921050022
Revert "riscv: mm: notify remote harts about mmu cache updates"
This reverts the remaining bits of commit 4bd1d80efb ("riscv: mm:
notify remote harts harts about mmu cache updates").

According to bug reports, suggested approach to fix stale TLB entries
is not sufficient. It needs to be replaced by a more robust solution.

Fixes: 4bd1d80efb ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: Zong Li <zong.li@sifive.com>
Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Cc: stable@vger.kernel.org
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230226150137.1919750-2-geomatsi@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-09 15:22:01 -08:00
..
asm Revert "riscv: mm: notify remote harts about mmu cache updates" 2023-03-09 15:22:01 -08:00
uapi/asm KVM/riscv changes for 6.2 2022-12-21 18:52:15 -08:00