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6cdf65855c
If there is a problem then this is hiding it, we shouldn't ever need to flush the IB. Either the buffers are: WB - caching just works. WC - no need to do explicit flush, the MB + readback will do it Signed-off-by: Dave Airlie <airlied@redhat.com>
473 lines
12 KiB
C
473 lines
12 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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int radeon_debugfs_ib_init(struct radeon_device *rdev);
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/*
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* IB.
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*/
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int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
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{
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struct radeon_fence *fence;
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struct radeon_ib *nib;
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unsigned long i;
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int r = 0;
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*ib = NULL;
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r = radeon_fence_create(rdev, &fence);
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if (r) {
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DRM_ERROR("failed to create fence for new IB\n");
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return r;
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}
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mutex_lock(&rdev->ib_pool.mutex);
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i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
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if (i < RADEON_IB_POOL_SIZE) {
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set_bit(i, rdev->ib_pool.alloc_bm);
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rdev->ib_pool.ibs[i].length_dw = 0;
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*ib = &rdev->ib_pool.ibs[i];
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goto out;
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}
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if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
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/* we go do nothings here */
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DRM_ERROR("all IB allocated none scheduled.\n");
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r = -EINVAL;
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goto out;
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}
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/* get the first ib on the scheduled list */
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nib = list_entry(rdev->ib_pool.scheduled_ibs.next,
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struct radeon_ib, list);
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if (nib->fence == NULL) {
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/* we go do nothings here */
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DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
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r = -EINVAL;
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goto out;
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}
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r = radeon_fence_wait(nib->fence, false);
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if (r) {
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DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
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(unsigned long)nib->gpu_addr, nib->length_dw);
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DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");
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goto out;
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}
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radeon_fence_unref(&nib->fence);
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nib->length_dw = 0;
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list_del(&nib->list);
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INIT_LIST_HEAD(&nib->list);
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*ib = nib;
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out:
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mutex_unlock(&rdev->ib_pool.mutex);
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if (r) {
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radeon_fence_unref(&fence);
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} else {
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(*ib)->fence = fence;
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}
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return r;
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}
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
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{
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struct radeon_ib *tmp = *ib;
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*ib = NULL;
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if (tmp == NULL) {
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return;
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}
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mutex_lock(&rdev->ib_pool.mutex);
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if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {
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/* IB is scheduled & not signaled don't do anythings */
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mutex_unlock(&rdev->ib_pool.mutex);
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return;
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}
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list_del(&tmp->list);
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INIT_LIST_HEAD(&tmp->list);
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if (tmp->fence) {
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radeon_fence_unref(&tmp->fence);
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}
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tmp->length_dw = 0;
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clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
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mutex_unlock(&rdev->ib_pool.mutex);
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}
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static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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while ((ib->length_dw & rdev->cp.align_mask)) {
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ib->ptr[ib->length_dw++] = PACKET2(0);
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}
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}
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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int r = 0;
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mutex_lock(&rdev->ib_pool.mutex);
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radeon_ib_align(rdev, ib);
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if (!ib->length_dw || !rdev->cp.ready) {
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/* TODO: Nothings in the ib we should report. */
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mutex_unlock(&rdev->ib_pool.mutex);
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DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
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return -EINVAL;
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}
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/* 64 dwords should be enough for fence too */
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r = radeon_ring_lock(rdev, 64);
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if (r) {
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DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
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mutex_unlock(&rdev->ib_pool.mutex);
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return r;
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}
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radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
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radeon_ring_write(rdev, ib->gpu_addr);
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radeon_ring_write(rdev, ib->length_dw);
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radeon_fence_emit(rdev, ib->fence);
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radeon_ring_unlock_commit(rdev);
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list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
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mutex_unlock(&rdev->ib_pool.mutex);
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return 0;
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}
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int radeon_ib_pool_init(struct radeon_device *rdev)
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{
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void *ptr;
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uint64_t gpu_addr;
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int i;
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int r = 0;
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/* Allocate 1M object buffer */
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INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
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r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
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true, RADEON_GEM_DOMAIN_GTT,
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false, &rdev->ib_pool.robj);
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if (r) {
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DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
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return r;
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}
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r = radeon_object_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
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if (r) {
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DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
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return r;
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}
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r = radeon_object_kmap(rdev->ib_pool.robj, &ptr);
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if (r) {
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DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
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return r;
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}
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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unsigned offset;
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offset = i * 64 * 1024;
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rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
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rdev->ib_pool.ibs[i].ptr = ptr + offset;
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rdev->ib_pool.ibs[i].idx = i;
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rdev->ib_pool.ibs[i].length_dw = 0;
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INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);
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}
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bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
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rdev->ib_pool.ready = true;
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DRM_INFO("radeon: ib pool ready.\n");
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if (radeon_debugfs_ib_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for IB !\n");
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}
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return r;
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}
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void radeon_ib_pool_fini(struct radeon_device *rdev)
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{
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if (!rdev->ib_pool.ready) {
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return;
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}
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mutex_lock(&rdev->ib_pool.mutex);
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bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
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if (rdev->ib_pool.robj) {
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radeon_object_kunmap(rdev->ib_pool.robj);
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radeon_object_unref(&rdev->ib_pool.robj);
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rdev->ib_pool.robj = NULL;
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}
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mutex_unlock(&rdev->ib_pool.mutex);
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}
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int radeon_ib_test(struct radeon_device *rdev)
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{
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struct radeon_ib *ib;
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uint32_t scratch;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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r = radeon_scratch_get(rdev, &scratch);
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if (r) {
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DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
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return r;
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}
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WREG32(scratch, 0xCAFEDEAD);
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r = radeon_ib_get(rdev, &ib);
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if (r) {
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return r;
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}
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ib->ptr[0] = PACKET0(scratch, 0);
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ib->ptr[1] = 0xDEADBEEF;
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ib->ptr[2] = PACKET2(0);
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ib->ptr[3] = PACKET2(0);
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ib->ptr[4] = PACKET2(0);
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ib->ptr[5] = PACKET2(0);
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ib->ptr[6] = PACKET2(0);
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ib->ptr[7] = PACKET2(0);
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ib->length_dw = 8;
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r = radeon_ib_schedule(rdev, ib);
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if (r) {
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radeon_scratch_free(rdev, scratch);
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radeon_ib_free(rdev, &ib);
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return r;
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}
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r = radeon_fence_wait(ib->fence, false);
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if (r) {
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF) {
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break;
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}
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DRM_UDELAY(1);
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}
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if (i < rdev->usec_timeout) {
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DRM_INFO("ib test succeeded in %u usecs\n", i);
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} else {
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DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
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scratch, tmp);
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r = -EINVAL;
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}
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radeon_scratch_free(rdev, scratch);
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radeon_ib_free(rdev, &ib);
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return r;
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}
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/*
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* Ring.
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*/
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void radeon_ring_free_size(struct radeon_device *rdev)
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{
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rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
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/* This works because ring_size is a power of 2 */
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rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
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rdev->cp.ring_free_dw -= rdev->cp.wptr;
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rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
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if (!rdev->cp.ring_free_dw) {
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rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
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}
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}
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int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
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{
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int r;
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
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mutex_lock(&rdev->cp.mutex);
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while (ndw > (rdev->cp.ring_free_dw - 1)) {
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radeon_ring_free_size(rdev);
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if (ndw < rdev->cp.ring_free_dw) {
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break;
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}
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r = radeon_fence_wait_next(rdev);
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if (r) {
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mutex_unlock(&rdev->cp.mutex);
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return r;
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}
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}
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rdev->cp.count_dw = ndw;
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rdev->cp.wptr_old = rdev->cp.wptr;
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return 0;
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}
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void radeon_ring_unlock_commit(struct radeon_device *rdev)
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{
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unsigned count_dw_pad;
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unsigned i;
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/* We pad to match fetch size */
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count_dw_pad = (rdev->cp.align_mask + 1) -
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(rdev->cp.wptr & rdev->cp.align_mask);
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for (i = 0; i < count_dw_pad; i++) {
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radeon_ring_write(rdev, PACKET2(0));
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}
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DRM_MEMORYBARRIER();
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WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
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(void)RREG32(RADEON_CP_RB_WPTR);
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mutex_unlock(&rdev->cp.mutex);
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}
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void radeon_ring_unlock_undo(struct radeon_device *rdev)
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{
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rdev->cp.wptr = rdev->cp.wptr_old;
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mutex_unlock(&rdev->cp.mutex);
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}
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int radeon_ring_test(struct radeon_device *rdev)
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{
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uint32_t scratch;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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r = radeon_scratch_get(rdev, &scratch);
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if (r) {
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DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
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return r;
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}
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WREG32(scratch, 0xCAFEDEAD);
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r = radeon_ring_lock(rdev, 2);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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radeon_scratch_free(rdev, scratch);
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return r;
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}
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radeon_ring_write(rdev, PACKET0(scratch, 0));
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radeon_ring_write(rdev, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev);
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF) {
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break;
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}
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DRM_UDELAY(1);
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}
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if (i < rdev->usec_timeout) {
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DRM_INFO("ring test succeeded in %d usecs\n", i);
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} else {
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DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
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scratch, tmp);
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r = -EINVAL;
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}
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radeon_scratch_free(rdev, scratch);
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return r;
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}
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int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
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{
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int r;
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rdev->cp.ring_size = ring_size;
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/* Allocate ring buffer */
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if (rdev->cp.ring_obj == NULL) {
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r = radeon_object_create(rdev, NULL, rdev->cp.ring_size,
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true,
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RADEON_GEM_DOMAIN_GTT,
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false,
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&rdev->cp.ring_obj);
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if (r) {
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DRM_ERROR("radeon: failed to create ring buffer (%d).\n", r);
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mutex_unlock(&rdev->cp.mutex);
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return r;
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}
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r = radeon_object_pin(rdev->cp.ring_obj,
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RADEON_GEM_DOMAIN_GTT,
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&rdev->cp.gpu_addr);
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if (r) {
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DRM_ERROR("radeon: failed to pin ring buffer (%d).\n", r);
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mutex_unlock(&rdev->cp.mutex);
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return r;
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}
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r = radeon_object_kmap(rdev->cp.ring_obj,
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(void **)&rdev->cp.ring);
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if (r) {
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DRM_ERROR("radeon: failed to map ring buffer (%d).\n", r);
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mutex_unlock(&rdev->cp.mutex);
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return r;
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}
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}
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rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
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rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
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return 0;
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}
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void radeon_ring_fini(struct radeon_device *rdev)
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{
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mutex_lock(&rdev->cp.mutex);
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if (rdev->cp.ring_obj) {
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radeon_object_kunmap(rdev->cp.ring_obj);
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radeon_object_unpin(rdev->cp.ring_obj);
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radeon_object_unref(&rdev->cp.ring_obj);
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rdev->cp.ring = NULL;
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rdev->cp.ring_obj = NULL;
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}
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mutex_unlock(&rdev->cp.mutex);
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct radeon_ib *ib = node->info_ent->data;
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unsigned i;
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if (ib == NULL) {
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return 0;
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}
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seq_printf(m, "IB %04lu\n", ib->idx);
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seq_printf(m, "IB fence %p\n", ib->fence);
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seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
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for (i = 0; i < ib->length_dw; i++) {
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seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
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}
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return 0;
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}
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static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
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static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
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#endif
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int radeon_debugfs_ib_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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unsigned i;
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
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radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
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radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
|
|
radeon_debugfs_ib_list[i].driver_features = 0;
|
|
radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
|
|
}
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
|
|
RADEON_IB_POOL_SIZE);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|