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For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least 4 times as often as other events. Due to byte counters will count for any event configured, it will overflow more often. And if byte counters overflow that related counters would stop since they share the COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting counter parameter (CP) field of cycle counter. In this way, we can avoid stop counting byte counters when interrupt didn't come and the byte counters can be fetched or updated from each cycle counter overflow interrupt. Because we initialize CP filed to shorten counter0 overflow time, the cycle counter will start couting from a fixed/base value each time. We need to remove the base from the result too. Therefore, we could get precise result from cycle counter. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230811015438.1999307-1-xu.yang_2@nxp.com Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| amlogic | ||
| arm_cspmu | ||
| hisilicon | ||
| alibaba_uncore_drw_pmu.c | ||
| apple_m1_cpu_pmu.c | ||
| arm_dmc620_pmu.c | ||
| arm_dsu_pmu.c | ||
| arm_pmu_acpi.c | ||
| arm_pmu_platform.c | ||
| arm_pmu.c | ||
| arm_pmuv3.c | ||
| arm_smmuv3_pmu.c | ||
| arm_spe_pmu.c | ||
| arm-cci.c | ||
| arm-ccn.c | ||
| arm-cmn.c | ||
| cxl_pmu.c | ||
| fsl_imx8_ddr_perf.c | ||
| fsl_imx9_ddr_perf.c | ||
| Kconfig | ||
| Makefile | ||
| marvell_cn10k_ddr_pmu.c | ||
| marvell_cn10k_tad_pmu.c | ||
| qcom_l2_pmu.c | ||
| qcom_l3_pmu.c | ||
| riscv_pmu_legacy.c | ||
| riscv_pmu_sbi.c | ||
| riscv_pmu.c | ||
| thunderx2_pmu.c | ||
| xgene_pmu.c | ||