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7b39e985cf
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
103 lines
2.5 KiB
C
103 lines
2.5 KiB
C
/*
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* Copyright (C) 2016 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
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#define __DT_BINDINGS_CLOCK_R8A7792_H__
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/* CPG */
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#define R8A7792_CLK_MAIN 0
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#define R8A7792_CLK_PLL0 1
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#define R8A7792_CLK_PLL1 2
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#define R8A7792_CLK_PLL3 3
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#define R8A7792_CLK_LB 4
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#define R8A7792_CLK_QSPI 5
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/* MSTP0 */
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#define R8A7792_CLK_MSIOF0 0
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/* MSTP1 */
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#define R8A7792_CLK_JPU 6
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#define R8A7792_CLK_TMU1 11
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#define R8A7792_CLK_TMU3 21
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#define R8A7792_CLK_TMU2 22
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#define R8A7792_CLK_CMT0 24
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#define R8A7792_CLK_TMU0 25
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#define R8A7792_CLK_VSP1DU1 27
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#define R8A7792_CLK_VSP1DU0 28
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#define R8A7792_CLK_VSP1_SY 31
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/* MSTP2 */
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#define R8A7792_CLK_MSIOF1 8
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#define R8A7792_CLK_SYS_DMAC1 18
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#define R8A7792_CLK_SYS_DMAC0 19
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/* MSTP3 */
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#define R8A7792_CLK_TPU0 4
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#define R8A7792_CLK_SDHI0 14
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#define R8A7792_CLK_CMT1 29
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/* MSTP4 */
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#define R8A7792_CLK_IRQC 7
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#define R8A7792_CLK_INTC_SYS 8
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/* MSTP5 */
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#define R8A7792_CLK_AUDIO_DMAC0 2
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#define R8A7792_CLK_THERMAL 22
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#define R8A7792_CLK_PWM 23
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/* MSTP7 */
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#define R8A7792_CLK_HSCIF1 16
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#define R8A7792_CLK_HSCIF0 17
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#define R8A7792_CLK_SCIF3 18
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#define R8A7792_CLK_SCIF2 19
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#define R8A7792_CLK_SCIF1 20
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#define R8A7792_CLK_SCIF0 21
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#define R8A7792_CLK_DU1 23
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#define R8A7792_CLK_DU0 24
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/* MSTP8 */
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#define R8A7792_CLK_VIN5 4
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#define R8A7792_CLK_VIN4 5
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#define R8A7792_CLK_VIN3 8
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#define R8A7792_CLK_VIN2 9
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#define R8A7792_CLK_VIN1 10
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#define R8A7792_CLK_VIN0 11
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#define R8A7792_CLK_ETHERAVB 12
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/* MSTP9 */
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#define R8A7792_CLK_GPIO7 4
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#define R8A7792_CLK_GPIO6 5
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#define R8A7792_CLK_GPIO5 7
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#define R8A7792_CLK_GPIO4 8
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#define R8A7792_CLK_GPIO3 9
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#define R8A7792_CLK_GPIO2 10
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#define R8A7792_CLK_GPIO1 11
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#define R8A7792_CLK_GPIO0 12
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#define R8A7792_CLK_GPIO11 13
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#define R8A7792_CLK_GPIO10 14
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#define R8A7792_CLK_CAN1 15
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#define R8A7792_CLK_CAN0 16
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#define R8A7792_CLK_QSPI_MOD 17
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#define R8A7792_CLK_GPIO9 19
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#define R8A7792_CLK_GPIO8 21
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#define R8A7792_CLK_I2C5 25
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#define R8A7792_CLK_IICDVFS 26
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#define R8A7792_CLK_I2C4 27
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#define R8A7792_CLK_I2C3 28
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#define R8A7792_CLK_I2C2 29
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#define R8A7792_CLK_I2C1 30
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#define R8A7792_CLK_I2C0 31
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/* MSTP10 */
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#define R8A7792_CLK_SSI_ALL 5
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#define R8A7792_CLK_SSI4 11
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#define R8A7792_CLK_SSI3 12
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#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
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