mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-16 16:54:20 +08:00
92b58b3474
TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. The interface mode is selected by configuring the MII mode selection register(s) (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and bit fields placement in SCM are different between SoCs while fields meaning is the same. Historically CPSW external Port's interface mode selection configuration was introduced using custom API and driver cpsw-phy-sel.c. This leads to unnecessary driver, DT binding and custom API support effort. This patch introduces CPSW Port's PHY Interface Mode selection Driver (phy-gmii-sel) which implements standard Linux PHY interface and used as a replacement for TI's specific driver cpsw-phy-sel.c and corresponding custom API. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
10 lines
418 B
Makefile
10 lines
418 B
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
|
|
obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
|
|
obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
|
|
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
|
|
obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
|
|
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
|
|
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
|
|
obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o
|