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f7f9da89bc
The clock controller registers are not 0x460 wide because the reset
controller starts at CBUS 0x4404. This currently overlaps with the
clock controller (which is at CBUS 0x4000).
There is no public documentation available on the actual size of the
clock controller's register area (also called "HHI"). However, in
Amlogic's GPL kernel sources the last "HHI" register is
HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
doesn't seem unlikely.
Fixes: 2c323c43a3 ("ARM: dts: meson8: add and use the real clock controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
427 lines
10 KiB
Plaintext
427 lines
10 KiB
Plaintext
/*
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* Copyright 2014 Carlo Caione <carlo@caione.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8-gpio.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#include <dt-bindings/reset/amlogic,meson8b-reset.h>
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#include "meson.dtsi"
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/ {
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model = "Amlogic Meson8 SoC";
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compatible = "amlogic,meson8";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x200>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
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};
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cpu1: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x201>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
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};
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cpu2: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x202>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
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};
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cpu3: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x203>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* 2 MiB reserved for Hardware ROM Firmware? */
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hwrom@0 {
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reg = <0x0 0x200000>;
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no-map;
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};
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/*
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* 1 MiB reserved for the "ARM Power Firmware": this is ARM
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* code which is responsible for system suspend. It loads a
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* piece of ARC code ("arc_power" in the vendor u-boot tree)
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* into SRAM, executes that and shuts down the (last) ARM core.
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* The arc_power firmware then checks various wakeup sources
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* (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
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* simply the power key) and re-starts the ARM core once it
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* detects a wakeup request.
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*/
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power-firmware@4f00000 {
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reg = <0x4f00000 0x100000>;
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no-map;
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};
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};
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scu@c4300000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xc4300000 0x100>;
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};
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}; /* end of / */
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&aobus {
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pmu: pmu@e0 {
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compatible = "amlogic,meson8-pmu", "syscon";
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reg = <0xe0 0x8>;
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};
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pinctrl_aobus: pinctrl@84 {
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compatible = "amlogic,meson8-aobus-pinctrl";
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reg = <0x84 0xc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio_ao: ao-bank@14 {
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reg = <0x14 0x4>,
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<0x2c 0x4>,
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<0x24 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 16>;
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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};
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};
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i2c_ao_pins: i2c_mst_ao {
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mux {
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groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
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function = "i2c_mst_ao";
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};
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};
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ir_recv_pins: remote {
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mux {
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groups = "remote_input";
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function = "remote";
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};
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};
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pwm_f_ao_pins: pwm-f-ao {
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mux {
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groups = "pwm_f_ao";
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function = "pwm_f_ao";
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};
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};
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};
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};
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&cbus {
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clkc: clock-controller@4000 {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "amlogic,meson8-clkc";
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reg = <0x8000 0x4>, <0x4000 0x400>;
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};
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reset: reset-controller@4404 {
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compatible = "amlogic,meson8b-reset";
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reg = <0x4404 0x9c>;
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#reset-cells = <1>;
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};
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analog_top: analog-top@81a8 {
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compatible = "amlogic,meson8-analog-top", "syscon";
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reg = <0x81a8 0x14>;
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
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reg = <0x86c0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pinctrl_cbus: pinctrl@9880 {
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compatible = "amlogic,meson8-cbus-pinctrl";
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reg = <0x9880 0x10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio: banks@80b0 {
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reg = <0x80b0 0x28>,
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<0x80e8 0x18>,
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<0x8120 0x18>,
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<0x8030 0x30>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_cbus 0 0 120>;
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};
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sd_a_pins: sd-a {
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mux {
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groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
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"sd_d3_a", "sd_clk_a", "sd_cmd_a";
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function = "sd_a";
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};
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};
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sd_b_pins: sd-b {
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mux {
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groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
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"sd_d3_b", "sd_clk_b", "sd_cmd_b";
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function = "sd_b";
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};
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};
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sd_c_pins: sd-c {
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mux {
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groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
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"sd_d3_c", "sd_clk_c", "sd_cmd_c";
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function = "sd_c";
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};
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};
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spi_nor_pins: nor {
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mux {
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groups = "nor_d", "nor_q", "nor_c", "nor_cs";
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function = "nor";
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};
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};
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eth_pins: ethernet {
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mux {
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groups = "eth_tx_clk_50m", "eth_tx_en",
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"eth_txd1", "eth_txd0",
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"eth_rx_clk_in", "eth_rx_dv",
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"eth_rxd1", "eth_rxd0", "eth_mdio",
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"eth_mdc";
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function = "ethernet";
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};
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};
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pwm_e_pins: pwm-e {
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mux {
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groups = "pwm_e";
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function = "pwm_e";
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};
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};
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uart_a1_pins: uart-a1 {
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mux {
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groups = "uart_tx_a1",
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"uart_rx_a1";
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function = "uart_a";
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};
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};
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uart_a1_cts_rts_pins: uart-a1-cts-rts {
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mux {
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groups = "uart_cts_a1",
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"uart_rts_a1";
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function = "uart_a";
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};
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};
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};
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};
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&ahb_sram {
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smp-sram@1ff80 {
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compatible = "amlogic,meson8-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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&efuse {
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compatible = "amlogic,meson8-efuse";
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clocks = <&clkc CLKID_EFUSE>;
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clock-names = "core";
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};
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ðmac {
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clocks = <&clkc CLKID_ETH>;
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clock-names = "stmmaceth";
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};
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&gpio_intc {
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compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
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status = "okay";
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};
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&hwrng {
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compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
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clocks = <&clkc CLKID_RNG0>;
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clock-names = "core";
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};
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&i2c_AO {
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clocks = <&clkc CLKID_CLK81>;
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};
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&i2c_A {
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clocks = <&clkc CLKID_CLK81>;
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};
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&i2c_B {
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clocks = <&clkc CLKID_CLK81>;
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};
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&L2 {
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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arm,filter-ranges = <0x100000 0xc0000000>;
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prefetch-data = <1>;
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prefetch-instr = <1>;
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arm,shared-override;
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};
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&pwm_ab {
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compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
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};
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&pwm_cd {
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compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
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};
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&saradc {
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compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
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clocks = <&clkc CLKID_XTAL>,
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<&clkc CLKID_SAR_ADC>;
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clock-names = "clkin", "core";
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};
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&sdio {
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compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
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clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
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clock-names = "core", "clkin";
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};
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&spifc {
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clocks = <&clkc CLKID_CLK81>;
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};
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&uart_AO {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_A {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_B {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_C {
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compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
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clock-names = "baud", "xtal", "pclk";
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};
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&usb0 {
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compatible = "amlogic,meson8-usb", "snps,dwc2";
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clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
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clock-names = "otg";
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};
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&usb1 {
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compatible = "amlogic,meson8-usb", "snps,dwc2";
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clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
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clock-names = "otg";
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};
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&usb0_phy {
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compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
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clock-names = "usb_general", "usb";
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resets = <&reset RESET_USB_OTG>;
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};
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&usb1_phy {
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compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
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clock-names = "usb_general", "usb";
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resets = <&reset RESET_USB_OTG>;
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};
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