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Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver. As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the support for revision 1.2 with chicken bit set. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
107 lines
2.3 KiB
C
107 lines
2.3 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "hardware.h"
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#define SCU_STANDBY_ENABLE (1 << 5)
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static void __iomem *scu_base;
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static struct map_desc scu_io_desc __initdata = {
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/* .virtual and .pfn are run-time assigned */
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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void __init imx_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.virtual = IMX_IO_P2V(base);
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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scu_base = IMX_IO_ADDRESS(base);
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}
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void imx_scu_standby_enable(void)
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{
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u32 val = readl_relaxed(scu_base);
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val |= SCU_STANDBY_ENABLE;
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writel_relaxed(val, scu_base);
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}
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static void __cpuinit imx_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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imx_set_cpu_jump(cpu, v7_secondary_startup);
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imx_enable_cpu(cpu, true);
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init imx_smp_init_cpus(void)
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{
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int i, ncores;
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ncores = scu_get_core_count(scu_base);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void imx_smp_prepare(void)
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{
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scu_enable(scu_base);
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}
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static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
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{
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imx_smp_prepare();
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}
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struct smp_operations imx_smp_ops __initdata = {
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.smp_init_cpus = imx_smp_init_cpus,
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.smp_prepare_cpus = imx_smp_prepare_cpus,
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.smp_secondary_init = imx_secondary_init,
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.smp_boot_secondary = imx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = imx_cpu_die,
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#endif
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};
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