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354fc6c513
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
16 lines
450 B
C
16 lines
450 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
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/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
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#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
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#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
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#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
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#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
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#endif
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