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9ddcd920f8
The PCIe QMP 4x2 RC PHY generates high latency when ASPM is enabled. This
seem to be fixed by clearing the QPHY_V5_20_PCS_PCIE_PRESET_P10_POST
register of the pcs_misc register space.
Fixes: 2c91bf6bf2 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
20 lines
665 B
C
20 lines
665 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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/* Only for QMP V5_20 PHY - PCIe PCS registers */
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#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
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#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
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#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
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#endif
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