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d79e9d7c1e
The correct setting for the RGMII ports on LS1046ARDB is to enable delay on both Rx and Tx so the interface mode used must be PHY_INTERFACE_MODE_RGMII_ID. Since commit1b3047b520("net: phy: realtek: add support for configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver has control over the RGMII RX delay and it is disabling it for RGMII_TXID. The LS1046ARDB uses two such PHYs in RGMII_ID mode but in the device tree the mode was described as "rgmii". Changing the phy-connection-type to "rgmii-id" to address the issue. Fixes:3fa395d2c4("arm64: dts: add LS1046A DPAA FMan nodes") Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
188 lines
2.8 KiB
Plaintext
188 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* Mingkai Hu <mingkai.hu@nxp.com>
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*/
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/dts-v1/;
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#include "fsl-ls1046a.dtsi"
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/ {
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model = "LS1046A RDB Board";
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compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
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aliases {
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serial0 = &duart0;
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serial1 = &duart1;
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serial2 = &duart2;
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serial3 = &duart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&esdhc {
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mmc-hs200-1_8v;
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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sd-uhs-sdr25;
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sd-uhs-sdr12;
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};
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&i2c0 {
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status = "okay";
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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temp-sensor@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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eeprom@52 {
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compatible = "atmel,24c512";
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reg = <0x52>;
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};
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eeprom@53 {
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compatible = "atmel,24c512";
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reg = <0x53>;
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};
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};
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&i2c3 {
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status = "okay";
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NAND Flashe and CPLD on board */
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ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
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0x2 0x0 0x0 0x7fb00000 0x00000100>;
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status = "okay";
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nand@0,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x0 0x10000>;
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};
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cpld: board-control@2,0 {
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compatible = "fsl,ls1046ardb-cpld";
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reg = <0x2 0x0 0x0000100>;
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};
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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reg = <0>;
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};
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s25fs512s1: flash@1 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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reg = <1>;
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};
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};
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&usb1 {
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dr_mode = "otg";
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};
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#include "fsl-ls1046-post.dtsi"
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&fman0 {
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@e8000 {
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phy-handle = <&sgmii_phy1>;
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phy-connection-type = "sgmii";
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};
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ethernet@ea000 {
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 { /* 10GEC1 */
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phy-handle = <&aqr106_phy>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 { /* 10GEC2 */
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fixed-link = <0 1 1000 0 0>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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sgmii_phy1: ethernet-phy@3 {
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reg = <0x3>;
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};
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sgmii_phy2: ethernet-phy@4 {
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reg = <0x4>;
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};
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};
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mdio@fd000 {
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aqr106_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <0 131 4>;
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reg = <0x0>;
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};
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};
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};
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