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bbaad14423
Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
96 lines
2.1 KiB
Plaintext
96 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "socionext,sc2000a";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "socionext,milbeaut-m10v-smp";
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cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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};
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cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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};
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cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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};
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};
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timer { /* The Generic Timer */
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <40000000>;
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always-on;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&gic>;
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gic: interrupt-controller@1d000000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1d001000 0x1000>,
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<0x1d002000 0x1000>; /* CPU I/f base and size */
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};
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timer@1e000050 { /* 32-bit Reload Timers */
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compatible = "socionext,milbeaut-timer";
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reg = <0x1e000050 0x20>;
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interrupts = <0 91 4>;
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};
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uart1: serial@1e700010 { /* PE4, PE5 */
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/* Enable this as ttyUSI0 */
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compatible = "socionext,milbeaut-usio-uart";
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reg = <0x1e700010 0x10>;
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interrupts = <0 141 0x4>, <0 149 0x4>;
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interrupt-names = "rx", "tx";
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};
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};
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sram@0 {
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compatible = "mmio-sram";
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reg = <0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x10000>;
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smp-sram@f100 {
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compatible = "socionext,milbeaut-smp-sram";
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reg = <0xf100 0x20>;
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};
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};
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};
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