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The suspend/resume code for Armada XP has to modify certain registers of the SDRAM controller. Therefore, we need to define a Device Tree binding for this hardware block. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: devicetree@vger.kernel.org Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
22 lines
628 B
Plaintext
22 lines
628 B
Plaintext
Device Tree bindings for MVEBU SDRAM controllers
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The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
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differs from one SoC variant to another, but they also share a number
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of commonalities.
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For now, this Device Tree binding documentation only documents the
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Armada XP SDRAM controller.
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Required properties:
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- compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
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- reg: a resource specifier for the register space, which should
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include all SDRAM controller registers as per the datasheet.
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Example:
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sdramc@1400 {
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compatible = "marvell,armada-xp-sdram-controller";
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reg = <0x1400 0x500>;
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};
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