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fa63c00397
dra76x is not affected by i887 which requires mmc3 node to be limited to
a max frequency of 64 MHz. Fix this by overwriting the correct value in
the the dra76 specific dtsi.
Fixes: 895bd4b3e5 ("ARM: dts: Add support for dra76-evm")
Cc: stable@vger.kernel.org
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
136 lines
3.1 KiB
Plaintext
136 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "dra74x.dtsi"
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/ {
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compatible = "ti,dra762", "ti,dra7";
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ocp {
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target-module@42c01900 {
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compatible = "ti,sysc-dra7-mcan", "ti,sysc";
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ranges = <0x0 0x42c00000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42c01900 0x4>,
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<0x42c01904 0x4>,
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<0x42c01908 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
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SYSC_DRA7_MCAN_ENAWAKEUP)>;
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ti,syss-mask = <1>;
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clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
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clock-names = "fck";
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m_can0: mcan@1a00 {
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compatible = "bosch,m_can";
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reg = <0x1a00 0x4000>, <0x0 0x18FC>;
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reg-names = "m_can", "message_ram";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&mcan_clk>, <&l3_iclk_div>;
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clock-names = "cclk", "hclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
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};
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};
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};
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};
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&l4_per3 {
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target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x1b0000 0x4>,
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<0x1b0010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1b0000 0x10000>;
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cal: cal@0 {
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compatible = "ti,dra76-cal";
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reg = <0x0000 0x400>,
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<0x0800 0x40>,
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<0x0900 0x40>;
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reg-names = "cal_top",
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"cal_rx_core0",
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"cal_rx_core1";
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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ti,camerrx-control = <&scm_conf 0x6dc>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi2_0: port@0 {
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reg = <0>;
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};
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csi2_1: port@1 {
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reg = <1>;
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};
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};
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};
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};
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};
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/* MCAN interrupts are hard-wired to irqs 67, 68 */
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&crossbar_mpu {
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ti,irqs-skip = <10 67 68 133 139 140>;
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};
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&scm_conf_clocks {
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dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_gmac_x2_ck>;
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ti,max-div = <63>;
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reg = <0x03fc>;
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ti,bit-shift=<20>;
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ti,latch-bit=<26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
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assigned-clock-rates = <80000000>;
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};
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dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
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reg = <0x3fc>;
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ti,bit-shift = <29>;
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ti,latch-bit=<26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
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};
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mcan_clk: mcan_clk@3fc {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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ti,bit-shift = <27>;
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reg = <0x3fc>;
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};
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};
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&rtctarget {
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status = "disabled";
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};
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&usb4_tm {
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status = "disabled";
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};
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&mmc3 {
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/* dra76x is not affected by i887 */
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max-frequency = <96000000>;
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};
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