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E810-T adapters have two external bidirectional SMA connectors and two internal unidirectional U.FL connectors. Multiplexing between U.FL and SMA and SMA direction is controlled using the PCA9575 expander. Add support for the PCA9575 detection and control of the respective pins of the SMA/U.FL multiplexer using the GPIO AQ API. Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com> Tested-by: Sunitha Mekala <sunithax.d.mekala@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021, Intel Corporation. */
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#ifndef _ICE_PTP_HW_H_
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#define _ICE_PTP_HW_H_
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enum ice_ptp_tmr_cmd {
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INIT_TIME,
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INIT_INCVAL,
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ADJ_TIME,
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ADJ_TIME_AT_TIME,
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READ_TIME
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};
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/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
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* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
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*/
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#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
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/* Device agnostic functions */
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u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
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bool ice_ptp_lock(struct ice_hw *hw);
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void ice_ptp_unlock(struct ice_hw *hw);
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int ice_ptp_init_time(struct ice_hw *hw, u64 time);
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int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
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int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
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int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
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int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
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int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
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/* E810 family functions */
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int ice_ptp_init_phy_e810(struct ice_hw *hw);
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int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
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int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
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bool ice_is_pca9575_present(struct ice_hw *hw);
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#define PFTSYN_SEM_BYTES 4
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/* PHY timer commands */
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#define SEL_CPK_SRC 8
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/* Time Sync command Definitions */
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#define GLTSYN_CMD_INIT_TIME BIT(0)
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#define GLTSYN_CMD_INIT_INCVAL BIT(1)
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#define GLTSYN_CMD_ADJ_TIME BIT(2)
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#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
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#define GLTSYN_CMD_READ_TIME BIT(7)
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#define TS_CMD_MASK_E810 0xFF
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#define SYNC_EXEC_CMD 0x3
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/* E810 timesync enable register */
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#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
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/* E810 shadow init time registers */
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#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
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#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
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/* E810 shadow time adjust registers */
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#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
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#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
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/* E810 timer command register */
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#define ETH_GLTSYN_CMD 0x03000344
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/* Source timer incval macros */
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#define INCVAL_HIGH_M 0xFF
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/* Timestamp block macros */
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#define TS_LOW_M 0xFFFFFFFF
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#define TS_HIGH_S 32
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#define BYTES_PER_IDX_ADDR_L_U 8
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/* External PHY timestamp address */
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#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
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((idx) * BYTES_PER_IDX_ADDR_L_U))
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#define LOW_TX_MEMORY_BANK_START 0x03090000
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#define HIGH_TX_MEMORY_BANK_START 0x03090004
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/* E810T SMA controller pin control */
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#define ICE_SMA1_DIR_EN_E810T BIT(4)
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#define ICE_SMA1_TX_EN_E810T BIT(5)
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#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
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#define ICE_SMA2_DIR_EN_E810T BIT(6)
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#define ICE_SMA2_TX_EN_E810T BIT(7)
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#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
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ICE_SMA1_TX_EN_E810T)
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#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
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ICE_SMA2_DIR_EN_E810T | \
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ICE_SMA2_TX_EN_E810T)
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#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
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ICE_SMA2_MASK_E810T)
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#define ICE_SMA_MIN_BIT_E810T 3
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#define ICE_SMA_MAX_BIT_E810T 7
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#define ICE_PCA9575_P1_OFFSET 8
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#endif /* _ICE_PTP_HW_H_ */
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