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A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZSvaJQAKCRB4tDGHoIJi 0sg6AQDQXrn1qqG+Gnq3uRl9on9KXf8xX16vcZrkzu+V8Qo2SgD/XnT8gJ5W3NwG y1XqbQ4HXIkhU1ETcanjL2zNL59IGgA= =IneL -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUtp6IACgkQYKtH/8kJ UicBmQ//eaXzVEB1LVP7Wt+jsUy5BLSlWm+Y/pDlSUyv7XJVILNUh20vmBmx/72a j70PCO7MegYUpH9jfg64QV8h4e0fdp6N+wPPMA0sUSdjl1J04Ad8+xIVbnCCytvF N1+aVnWpaX4h+UF739hi7A0J5TAd2CEKSicQ5B3eAeWjHxfOdwE4eu08PstL7WZD yCI7UDRb2vYs5+l0gNk0PjJ6ngR8tivlgtOlaW1fkvT1L7s4ij7XWVXFMN6JjlPD A1dJeuaeOUXWUR4ow71IXMBWxzflQ4hZL++yqeHtRxxw09BUDTtV4gNhJgnGgq7I EN5SZ8cLKASYc2+Z6DUU2m2niYz4Au2YdspzJMnDbuVTQSo9/Dwrbn36XgWygafD EmOKP75d70tWvNtZ/BoyCrGets81+6SYSubxEvHEm32RPKqSS2UQVy2h92s0mXfj 24V2klZs3PG2+k4Kt3gMOSliF03SbcI+lWglOrCAVb98mc43kQt02oNw/0icyane BPoyfQFrIXC5HT0E+iWXIP3fSLp1edLzxN/VqidPneBXGlLHxdspPrZP3zKFvQ6m 3Ncx2r/h8C4Spltf8eqvsGc5fkizYlIAq9hPUnXOIIwOaBgHwRfgIL5uq6LxD6wt SRRy+VyNJjtAHNyZJXSUZ8KQsMKVdvO/IOw9cGtiy/AiP0/a5EU= =QdXG -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes RISC-V Devicetrees for v6.6-final A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: visionfive 2: correct spi's ss pin Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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