mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-03 00:54:09 +08:00
187bea4726
When CONFIG_FORTIFY_SOURCE is set, memcpy() checks the potential
buffer overflow and panics. The code in sofcpga bootstrapping
contains the memcpy() calls are mistakenly translated as the shorter
size, hence it triggers a panic as if it were overflowing.
This patch changes the secondary_trampoline and *_end definitions
to arrays for avoiding the false-positive crash above.
Fixes: 9c4566a117 ("ARM: socfpga: Enable SMP for socfpga")
Suggested-by: Kees Cook <keescook@chromium.org>
Buglink: https://bugzilla.suse.com/show_bug.cgi?id=1192473
Link: https://lore.kernel.org/r/20211117193244.31162-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* Copyright 2012 Pavel Machek <pavel@denx.de>
|
|
* Copyright (C) 2012-2015 Altera Corporation
|
|
*/
|
|
|
|
#ifndef __MACH_CORE_H
|
|
#define __MACH_CORE_H
|
|
|
|
#define SOCFPGA_RSTMGR_CTRL 0x04
|
|
#define SOCFPGA_RSTMGR_MODMPURST 0x10
|
|
#define SOCFPGA_RSTMGR_MODPERRST 0x14
|
|
#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
|
|
|
|
#define SOCFPGA_A10_RSTMGR_CTRL 0xC
|
|
#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
|
|
|
|
/* System Manager bits */
|
|
#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
|
|
#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
|
|
|
|
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
|
|
|
|
void socfpga_init_l2_ecc(void);
|
|
void socfpga_init_ocram_ecc(void);
|
|
void socfpga_init_arria10_l2_ecc(void);
|
|
void socfpga_init_arria10_ocram_ecc(void);
|
|
|
|
extern void __iomem *sys_manager_base_addr;
|
|
extern void __iomem *rst_manager_base_addr;
|
|
extern void __iomem *sdr_ctl_base_addr;
|
|
|
|
u32 socfpga_sdram_self_refresh(u32 sdr_base);
|
|
extern unsigned int socfpga_sdram_self_refresh_sz;
|
|
|
|
extern char secondary_trampoline[], secondary_trampoline_end[];
|
|
|
|
extern unsigned long socfpga_cpu1start_addr;
|
|
|
|
#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
|
|
|
|
#endif
|