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064520e8ae
Add platform abstraction for the Meteor Lake platform. This platform has significant differences compared to the TGL/ADL generation: it relies on new hardware using the code name 'ACE' and only supports the INTEL_IPC4 protocol and firmware architecture based on the Zephyr RTOS Co-developed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Link: https://lore.kernel.org/r/20220615084348.3489-3-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2020-2022 Intel Corporation. All rights reserved.
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*/
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/* DSP Registers */
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#define MTL_HFDSSCS 0x1000
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#define MTL_HFDSSCS_SPA_MASK BIT(16)
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#define MTL_HFDSSCS_CPA_MASK BIT(24)
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#define MTL_HFSNDWIE 0x114C
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#define MTL_HFPWRCTL 0x1D18
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#define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8)
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#define MTL_HFPWRCTL_WPDSPHPXPG BIT(0)
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#define MTL_HFPWRSTS 0x1D1C
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#define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0)
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#define MTL_HFINTIPPTR 0x1108
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#define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0)
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#define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK BIT(6)
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#define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0)
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#define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00
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#define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04
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#define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0)
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#define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8)
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#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24)
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#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24
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/* IPC Registers */
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#define MTL_DSP_REG_HFIPCXTDR 0x73200
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#define MTL_DSP_REG_HFIPCXTDR_BUSY BIT(31)
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#define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0)
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#define MTL_DSP_REG_HFIPCXTDA 0x73204
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#define MTL_DSP_REG_HFIPCXTDA_BUSY BIT(31)
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#define MTL_DSP_REG_HFIPCXIDR 0x73210
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#define MTL_DSP_REG_HFIPCXIDR_BUSY BIT(31)
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#define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0)
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#define MTL_DSP_REG_HFIPCXIDA 0x73214
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#define MTL_DSP_REG_HFIPCXIDA_DONE BIT(31)
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#define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0)
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#define MTL_DSP_REG_HFIPCXCTL 0x73228
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#define MTL_DSP_REG_HFIPCXCTL_BUSY BIT(0)
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#define MTL_DSP_REG_HFIPCXCTL_DONE BIT(1)
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#define MTL_DSP_REG_HFIPCXTDDY 0x73300
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#define MTL_DSP_REG_HFIPCXIDDY 0x73380
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#define MTL_DSP_REG_HfHIPCIE 0x1140
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#define MTL_DSP_REG_HfHIPCIE_IE_MASK BIT(0)
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#define MTL_DSP_REG_HfSNDWIE 0x114C
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#define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0)
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#define MTL_DSP_IRQSTS 0x20
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#define MTL_DSP_IRQSTS_IPC BIT(0)
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#define MTL_DSP_IRQSTS_SDW BIT(6)
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#define MTL_DSP_PURGE_TIMEOUT_US 20000000 /* 20s */
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#define MTL_DSP_REG_POLL_INTERVAL_US 10 /* 10 us */
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/* Memory windows */
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#define MTL_SRAM_WINDOW_OFFSET(x) (0x180000 + 0x8000 * (x))
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#define MTL_DSP_MBOX_UPLINK_OFFSET (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000)
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#define MTL_DSP_MBOX_UPLINK_SIZE 0x1000
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#define MTL_DSP_MBOX_DOWNLINK_OFFSET MTL_SRAM_WINDOW_OFFSET(1)
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#define MTL_DSP_MBOX_DOWNLINK_SIZE 0x1000
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/* FW registers */
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#define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
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#define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
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#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */
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#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */
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#define MTL_DSP_REG_HfIMRIS1 0x162088
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#define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0)
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