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2a152512a1
This patch adds support for CQ notifications through the standard verbs api. In order to achieve that, a new event queue (EQ) object is introduced, which is in charge of reporting completion events to the driver. On driver load, EQs are allocated and their affinity is set to a single cpu. When a user app creates a CQ with a completion channel, the completion vector number is converted to a EQ number, which is in charge of reporting the CQ events. In addition, the CQ creation admin command now returns an offset for the CQ doorbell, which is mapped to the userspace provider and is used to arm the CQ when requested by the user. The EQs use a single doorbell (located on the registers BAR), which encodes the EQ number and arm as part of the doorbell value. The EQs are polled by the driver on each new EQE, and arm it when the poll is completed. Link: https://lore.kernel.org/r/20211003105605.29222-1-galpress@amazon.com Reviewed-by: Firas JahJah <firasj@amazon.com> Reviewed-by: Yossi Leybovich <sleybo@amazon.com> Signed-off-by: Gal Pressman <galpress@amazon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
134 lines
2.7 KiB
C
134 lines
2.7 KiB
C
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
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/*
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* Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef EFA_ABI_USER_H
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#define EFA_ABI_USER_H
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#include <linux/types.h>
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/*
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* Increment this value if any changes that break userspace ABI
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* compatibility are made.
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*/
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#define EFA_UVERBS_ABI_VERSION 1
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/*
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* Keep structs aligned to 8 bytes.
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* Keep reserved fields as arrays of __u8 named reserved_XXX where XXX is the
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* hex bit offset of the field.
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*/
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enum {
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EFA_ALLOC_UCONTEXT_CMD_COMP_TX_BATCH = 1 << 0,
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EFA_ALLOC_UCONTEXT_CMD_COMP_MIN_SQ_WR = 1 << 1,
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};
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struct efa_ibv_alloc_ucontext_cmd {
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__u32 comp_mask;
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__u8 reserved_20[4];
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};
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enum efa_ibv_user_cmds_supp_udata {
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EFA_USER_CMDS_SUPP_UDATA_QUERY_DEVICE = 1 << 0,
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EFA_USER_CMDS_SUPP_UDATA_CREATE_AH = 1 << 1,
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};
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struct efa_ibv_alloc_ucontext_resp {
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__u32 comp_mask;
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__u32 cmds_supp_udata_mask;
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__u16 sub_cqs_per_cq;
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__u16 inline_buf_size;
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__u32 max_llq_size; /* bytes */
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__u16 max_tx_batch; /* units of 64 bytes */
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__u16 min_sq_wr;
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__u8 reserved_a0[4];
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};
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struct efa_ibv_alloc_pd_resp {
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__u32 comp_mask;
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__u16 pdn;
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__u8 reserved_30[2];
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};
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enum {
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EFA_CREATE_CQ_WITH_COMPLETION_CHANNEL = 1 << 0,
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};
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struct efa_ibv_create_cq {
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__u32 comp_mask;
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__u32 cq_entry_size;
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__u16 num_sub_cqs;
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__u8 flags;
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__u8 reserved_58[5];
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};
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enum {
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EFA_CREATE_CQ_RESP_DB_OFF = 1 << 0,
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};
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struct efa_ibv_create_cq_resp {
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__u32 comp_mask;
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__u8 reserved_20[4];
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__aligned_u64 q_mmap_key;
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__aligned_u64 q_mmap_size;
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__u16 cq_idx;
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__u8 reserved_d0[2];
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__u32 db_off;
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__aligned_u64 db_mmap_key;
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};
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enum {
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EFA_QP_DRIVER_TYPE_SRD = 0,
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};
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struct efa_ibv_create_qp {
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__u32 comp_mask;
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__u32 rq_ring_size; /* bytes */
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__u32 sq_ring_size; /* bytes */
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__u32 driver_qp_type;
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};
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struct efa_ibv_create_qp_resp {
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__u32 comp_mask;
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/* the offset inside the page of the rq db */
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__u32 rq_db_offset;
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/* the offset inside the page of the sq db */
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__u32 sq_db_offset;
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/* the offset inside the page of descriptors buffer */
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__u32 llq_desc_offset;
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__aligned_u64 rq_mmap_key;
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__aligned_u64 rq_mmap_size;
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__aligned_u64 rq_db_mmap_key;
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__aligned_u64 sq_db_mmap_key;
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__aligned_u64 llq_desc_mmap_key;
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__u16 send_sub_cq_idx;
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__u16 recv_sub_cq_idx;
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__u8 reserved_1e0[4];
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};
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struct efa_ibv_create_ah_resp {
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__u32 comp_mask;
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__u16 efa_address_handle;
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__u8 reserved_30[2];
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};
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enum {
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EFA_QUERY_DEVICE_CAPS_RDMA_READ = 1 << 0,
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EFA_QUERY_DEVICE_CAPS_RNR_RETRY = 1 << 1,
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EFA_QUERY_DEVICE_CAPS_CQ_NOTIFICATIONS = 1 << 2,
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};
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struct efa_ibv_ex_query_device_resp {
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__u32 comp_mask;
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__u32 max_sq_wr;
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__u32 max_rq_wr;
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__u16 max_sq_sge;
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__u16 max_rq_sge;
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__u32 max_rdma_size;
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__u32 device_caps;
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};
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#endif /* EFA_ABI_USER_H */
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