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3e4ea3728a
- Vectored Interrupt Controller support - Timer support using the GPT and DGT timers Signed-off-by: Brian Swetland <swetland@google.com>
155 lines
4.6 KiB
C
155 lines
4.6 KiB
C
/* linux/arch/arm/mach-msm/irq.c
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*
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/msm_iomap.h>
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#define VIC_REG(off) (MSM_VIC_BASE + (off))
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#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_EN0 VIC_REG(0x0010)
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#define VIC_INT_EN1 VIC_REG(0x0014)
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#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
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#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
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#define VIC_INT_ENSET0 VIC_REG(0x0030)
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#define VIC_INT_ENSET1 VIC_REG(0x0034)
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#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
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#define VIC_NO_PEND_VAL VIC_REG(0x0060)
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#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
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#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
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#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
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#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
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#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
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#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
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#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
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#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
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#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
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#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
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#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
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#define VIC_SOFTINT0 VIC_REG(0x00C0)
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#define VIC_SOFTINT1 VIC_REG(0x00C4)
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#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
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#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
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#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
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#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
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#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
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static void msm_irq_ack(unsigned int irq)
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{
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unsigned reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
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irq = 1 << (irq & 31);
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writel(irq, reg);
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}
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static void msm_irq_mask(unsigned int irq)
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{
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unsigned reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
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writel(1 << (irq & 31), reg);
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}
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static void msm_irq_unmask(unsigned int irq)
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{
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unsigned reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
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writel(1 << (irq & 31), reg);
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}
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static int msm_irq_set_wake(unsigned int irq, unsigned int on)
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{
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return -EINVAL;
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}
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static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
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unsigned preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
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int b = 1 << (irq & 31);
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if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
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writel(readl(preg) | b, preg);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
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writel(readl(preg) & (~b), preg);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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writel(readl(treg) | b, treg);
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set_irq_handler(irq, handle_edge_irq);
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}
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if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
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writel(readl(treg) & (~b), treg);
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set_irq_handler(irq, handle_level_irq);
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}
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return 0;
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}
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static struct irq_chip msm_irq_chip = {
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.name = "msm",
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.ack = msm_irq_ack,
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.mask = msm_irq_mask,
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.unmask = msm_irq_unmask,
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.set_wake = msm_irq_set_wake,
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.set_type = msm_irq_set_type,
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};
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void __init msm_init_irq(void)
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{
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unsigned n;
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/* select level interrupts */
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writel(0, VIC_INT_TYPE0);
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writel(0, VIC_INT_TYPE1);
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/* select highlevel interrupts */
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writel(0, VIC_INT_POLARITY0);
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writel(0, VIC_INT_POLARITY1);
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/* select IRQ for all INTs */
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writel(0, VIC_INT_SELECT0);
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writel(0, VIC_INT_SELECT1);
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/* disable all INTs */
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writel(0, VIC_INT_EN0);
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writel(0, VIC_INT_EN1);
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/* don't use 1136 vic */
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writel(0, VIC_CONFIG);
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/* enable interrupt controller */
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writel(1, VIC_INT_MASTEREN);
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for (n = 0; n < NR_MSM_IRQS; n++) {
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set_irq_chip(n, &msm_irq_chip);
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set_irq_handler(n, handle_level_irq);
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set_irq_flags(n, IRQF_VALID);
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}
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}
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