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The big.LITTLE architecture is composed of two clusters of cpus. One cluster contains less powerful but more energy efficient processors and the other cluster groups the powerful but energy-intensive cpus. The TC2 testchip implements two clusters of CPUs (A7 and A15 clusters in a big.LITTLE configuration) connected through a CCI interconnect that manages coherency of their respective L2 caches and intercluster distributed virtual memory messages (DVM). TC2 testchip integrates a power controller that manages cores resets, wake-up IRQs and cluster low-power states. Power states are managed at cluster level, which means that voltage is removed from a cluster iff all cores in a cluster are in a wfi state. Single cores can enter a reset state which is identical to wfi in terms of power consumption but simplifies the way cluster states are entered. This patch provides a multiple driver CPU idle implementation for TC2 which paves the way for a generic big.LITTLE idle driver for all upcoming big.LITTLE based systems on chip. The driver relies on the MCPM infrastructure to coordinate and manage core power states; in particular MCPM allows to suspend specific cores and hides the CPUs coordination required to shut-down clusters of CPUs. Power down sequences for the respective clusters are implemented in the MCPM TC2 backend, with all code needed to clean caches and exit coherency. The multiple driver CPU idle infrastructure allows to define different C-states for big and little cores, determined at boot by checking the part id of the possible CPUs and initializing the respective logical masks in the big and little drivers. Current big.little systems are composed of A7 and A15 clusters, as implemented in TC2, but in the future that may change and the driver will have evolve to retrieve what is a 'big' cpu and what is a 'little' cpu in order to build the correct topology. Cc: Kevin Hilman <khilman@linaro.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Olof Johansson <olof@lixom.net> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
43 lines
1.1 KiB
Plaintext
43 lines
1.1 KiB
Plaintext
menu "CPU Idle"
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config CPU_IDLE
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bool "CPU idle PM support"
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default y if ACPI || PPC_PSERIES
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select CPU_IDLE_GOV_LADDER if (!NO_HZ && !NO_HZ_IDLE)
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select CPU_IDLE_GOV_MENU if (NO_HZ || NO_HZ_IDLE)
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help
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CPU idle is a generic framework for supporting software-controlled
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idle processor power management. It includes modular cross-platform
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governors that can be swapped during runtime.
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If you're using an ACPI-enabled platform, you should say Y here.
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if CPU_IDLE
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config CPU_IDLE_MULTIPLE_DRIVERS
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bool "Support multiple cpuidle drivers"
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default n
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help
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Allows the cpuidle framework to use different drivers for each CPU.
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This is useful if you have a system with different CPU latencies and
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states. If unsure say N.
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config CPU_IDLE_GOV_LADDER
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bool "Ladder governor (for periodic timer tick)"
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default y
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config CPU_IDLE_GOV_MENU
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bool "Menu governor (for tickless system)"
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default y
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menu "ARM CPU Idle Drivers"
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depends on ARM
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source "drivers/cpuidle/Kconfig.arm"
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endmenu
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endif
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config ARCH_NEEDS_CPU_IDLE_COUPLED
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def_bool n
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endmenu
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