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This patch adds ptrace interface test for TM SPR registers. This also adds ptrace interface based helper functions related to TM SPR registers access. Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
169 lines
3.3 KiB
C
169 lines
3.3 KiB
C
/*
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* Ptrace test TM SPR registers
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*
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* Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include "ptrace.h"
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#include "tm.h"
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/* Tracee and tracer shared data */
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struct shared {
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int flag;
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struct tm_spr_regs regs;
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};
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unsigned long tfhar;
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int shm_id;
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struct shared *cptr, *pptr;
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int shm_id1;
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int *cptr1, *pptr1;
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#define TM_KVM_SCHED 0xe0000001ac000001
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int validate_tm_spr(struct tm_spr_regs *regs)
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{
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FAIL_IF(regs->tm_tfhar != tfhar);
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FAIL_IF((regs->tm_texasr == TM_KVM_SCHED) && (regs->tm_tfiar != 0));
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return TEST_PASS;
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}
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void tm_spr(void)
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{
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unsigned long result, texasr;
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int ret;
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cptr = (struct shared *)shmat(shm_id, NULL, 0);
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cptr1 = (int *)shmat(shm_id1, NULL, 0);
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trans:
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cptr1[0] = 0;
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asm __volatile__(
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"1: ;"
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/* TM failover handler should follow "tbegin.;" */
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"mflr 31;"
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"bl 4f;" /* $ = TFHAR - 12 */
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"4: ;"
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"mflr %[tfhar];"
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"mtlr 31;"
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"tbegin.;"
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"beq 2f;"
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"tsuspend.;"
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"li 8, 1;"
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"sth 8, 0(%[cptr1]);"
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"tresume.;"
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"b .;"
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"tend.;"
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"li 0, 0;"
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"ori %[res], 0, 0;"
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"b 3f;"
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"2: ;"
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"li 0, 1;"
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"ori %[res], 0, 0;"
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"mfspr %[texasr], %[sprn_texasr];"
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"3: ;"
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: [tfhar] "=r" (tfhar), [res] "=r" (result),
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[texasr] "=r" (texasr), [cptr1] "=r" (cptr1)
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: [sprn_texasr] "i" (SPRN_TEXASR)
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: "memory", "r0", "r1", "r2", "r3", "r4",
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"r8", "r9", "r10", "r11", "r31"
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);
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/* There are 2 32bit instructions before tbegin. */
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tfhar += 12;
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if (result) {
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if (!cptr->flag)
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goto trans;
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ret = validate_tm_spr((struct tm_spr_regs *)&cptr->regs);
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shmdt((void *)cptr);
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shmdt((void *)cptr1);
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if (ret)
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exit(1);
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exit(0);
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}
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shmdt((void *)cptr);
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shmdt((void *)cptr1);
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exit(1);
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}
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int trace_tm_spr(pid_t child)
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{
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FAIL_IF(start_trace(child));
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FAIL_IF(show_tm_spr(child, (struct tm_spr_regs *)&pptr->regs));
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printf("TFHAR: %lx TEXASR: %lx TFIAR: %lx\n", pptr->regs.tm_tfhar,
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pptr->regs.tm_texasr, pptr->regs.tm_tfiar);
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pptr->flag = 1;
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FAIL_IF(stop_trace(child));
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return TEST_PASS;
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}
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int ptrace_tm_spr(void)
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{
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pid_t pid;
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int ret, status;
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SKIP_IF(!have_htm());
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shm_id = shmget(IPC_PRIVATE, sizeof(struct shared), 0777|IPC_CREAT);
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shm_id1 = shmget(IPC_PRIVATE, sizeof(int), 0777|IPC_CREAT);
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pid = fork();
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if (pid < 0) {
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perror("fork() failed");
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return TEST_FAIL;
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}
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if (pid == 0)
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tm_spr();
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if (pid) {
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pptr = (struct shared *)shmat(shm_id, NULL, 0);
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pptr1 = (int *)shmat(shm_id1, NULL, 0);
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while (!pptr1[0])
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asm volatile("" : : : "memory");
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ret = trace_tm_spr(pid);
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if (ret) {
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kill(pid, SIGKILL);
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shmdt((void *)pptr);
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shmdt((void *)pptr1);
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shmctl(shm_id, IPC_RMID, NULL);
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shmctl(shm_id1, IPC_RMID, NULL);
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return TEST_FAIL;
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}
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shmdt((void *)pptr);
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shmdt((void *)pptr1);
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ret = wait(&status);
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shmctl(shm_id, IPC_RMID, NULL);
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shmctl(shm_id1, IPC_RMID, NULL);
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if (ret != pid) {
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printf("Child's exit status not captured\n");
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return TEST_FAIL;
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}
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return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL :
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TEST_PASS;
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}
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return TEST_PASS;
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}
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int main(int argc, char *argv[])
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{
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return test_harness(ptrace_tm_spr, "ptrace_tm_spr");
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}
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