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f0f59a00a1
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
118 lines
3.7 KiB
C
118 lines
3.7 KiB
C
/*
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* Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _I915_VGPU_H_
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#define _I915_VGPU_H_
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/* The MMIO offset of the shared info between guest and host emulator */
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#define VGT_PVINFO_PAGE 0x78000
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#define VGT_PVINFO_SIZE 0x1000
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/*
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* The following structure pages are defined in GEN MMIO space
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* for virtualization. (One page for now)
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*/
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#define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */
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#define VGT_VERSION_MAJOR 1
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#define VGT_VERSION_MINOR 0
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#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
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#define INTEL_VGT_IF_VERSION \
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INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
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/*
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* notifications from guest to vgpu device model
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*/
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enum vgt_g2v_type {
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VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
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VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
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VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
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VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
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VGT_G2V_EXECLIST_CONTEXT_CREATE,
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VGT_G2V_EXECLIST_CONTEXT_DESTROY,
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VGT_G2V_MAX,
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};
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struct vgt_if {
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uint64_t magic; /* VGT_MAGIC */
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uint16_t version_major;
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uint16_t version_minor;
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uint32_t vgt_id; /* ID of vGT instance */
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uint32_t rsv1[12]; /* pad to offset 0x40 */
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/*
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* Data structure to describe the balooning info of resources.
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* Each VM can only have one portion of continuous area for now.
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* (May support scattered resource in future)
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* (starting from offset 0x40)
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*/
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struct {
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/* Aperture register balooning */
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struct {
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uint32_t base;
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uint32_t size;
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} mappable_gmadr; /* aperture */
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/* GMADR register balooning */
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struct {
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uint32_t base;
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uint32_t size;
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} nonmappable_gmadr; /* non aperture */
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/* allowed fence registers */
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uint32_t fence_num;
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uint32_t rsv2[3];
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} avail_rs; /* available/assigned resource */
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uint32_t rsv3[0x200 - 24]; /* pad to half page */
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/*
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* The bottom half page is for response from Gfx driver to hypervisor.
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*/
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uint32_t rsv4;
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uint32_t display_ready; /* ready for display owner switch */
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uint32_t rsv5[4];
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uint32_t g2v_notify;
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uint32_t rsv6[7];
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struct {
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uint32_t lo;
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uint32_t hi;
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} pdp[4];
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uint32_t execlist_context_descriptor_lo;
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uint32_t execlist_context_descriptor_hi;
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uint32_t rsv7[0x200 - 24]; /* pad to one page */
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} __packed;
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#define vgtif_reg(x) \
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_MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
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/* vGPU display status to be used by the host side */
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#define VGT_DRV_DISPLAY_NOT_READY 0
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#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
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extern void i915_check_vgpu(struct drm_device *dev);
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extern int intel_vgt_balloon(struct drm_device *dev);
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extern void intel_vgt_deballoon(void);
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#endif /* _I915_VGPU_H_ */
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