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e1ea075423
Our attempts save/restore panel power state in i915_suspend.c are
causing unclaimed register warnings on BXT since the registers for this
platform differ from older platforms.
The big hammer suspend/resume shouldn't be necessary for PP since the
connector/encoder hooks should already handle this. In theory we could
remove this for all platforms, but in practice it's likely that would
cause some regressions since older platforms with LVDS may have
incomplete PP handling. For now we'll leave the PCH save/restore alone
and change the non-PCH branch to only operate on gen <= 4 so that BXT
and future platforms aren't included.
v2: Typo fix: s/||/&&/
v3: Change non-PCH condition to a gen <= 4 test rather than listing
VLV/CHV/BXT as specific platforms to exclude; should be more
future-proof as we add new platforms. (Daniel)
Cc: Vandana Kannan <vandana.kannan@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: drm-intel-fixes@lists.freedesktop.org
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1452102821-17190-1-git-send-email-matthew.d.roper@intel.com
197 lines
6.4 KiB
C
197 lines
6.4 KiB
C
/*
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*
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* Copyright 2008 (c) Intel Corporation
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "intel_drv.h"
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#include "i915_reg.h"
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static void i915_save_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* Display arbitration control */
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if (INTEL_INFO(dev)->gen <= 4)
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dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
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/* LVDS state */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
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else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
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dev_priv->regfile.saveLVDS = I915_READ(LVDS);
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/* Panel power sequencer */
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
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dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
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dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
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dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
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} else if (INTEL_INFO(dev)->gen <= 4) {
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dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
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dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
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dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
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dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
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}
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/* save FBC interval */
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
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dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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}
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static void i915_restore_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 mask = 0xffffffff;
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/* Display arbitration */
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if (INTEL_INFO(dev)->gen <= 4)
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I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
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mask = ~LVDS_PORT_EN;
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/* LVDS state */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
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else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
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I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
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/* Panel power sequencer */
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if (HAS_PCH_SPLIT(dev)) {
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I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
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I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
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I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
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I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
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} else if (INTEL_INFO(dev)->gen <= 4) {
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I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
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I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
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I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
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I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
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}
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/* only restore FBC info on the platform that supports FBC*/
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intel_fbc_global_disable(dev_priv);
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/* restore FBC interval */
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
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I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
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i915_redisable_vga(dev);
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}
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int i915_save_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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mutex_lock(&dev->struct_mutex);
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i915_save_display(dev);
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if (IS_GEN4(dev))
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pci_read_config_word(dev->pdev, GCDGMBUS,
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&dev_priv->regfile.saveGCDGMBUS);
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/* Cache mode state */
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if (INTEL_INFO(dev)->gen < 7)
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dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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/* Memory Arbitration state */
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dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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/* Scratch space */
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if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
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for (i = 0; i < 7; i++) {
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dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
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}
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for (i = 0; i < 3; i++)
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dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
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} else if (IS_GEN2(dev_priv)) {
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for (i = 0; i < 7; i++)
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
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} else if (HAS_GMCH_DISPLAY(dev_priv)) {
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for (i = 0; i < 16; i++) {
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dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
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}
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for (i = 0; i < 3; i++)
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dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
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}
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mutex_unlock(&dev->struct_mutex);
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return 0;
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}
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int i915_restore_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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mutex_lock(&dev->struct_mutex);
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i915_gem_restore_fences(dev);
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if (IS_GEN4(dev))
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pci_write_config_word(dev->pdev, GCDGMBUS,
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dev_priv->regfile.saveGCDGMBUS);
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i915_restore_display(dev);
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/* Cache mode state */
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if (INTEL_INFO(dev)->gen < 7)
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I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
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0xffff0000);
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/* Memory arbitration state */
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I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
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/* Scratch space */
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if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
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for (i = 0; i < 7; i++) {
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I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
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I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
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}
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for (i = 0; i < 3; i++)
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I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
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} else if (IS_GEN2(dev_priv)) {
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for (i = 0; i < 7; i++)
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I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
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} else if (HAS_GMCH_DISPLAY(dev_priv)) {
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for (i = 0; i < 16; i++) {
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I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
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I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
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}
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for (i = 0; i < 3; i++)
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I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
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}
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mutex_unlock(&dev->struct_mutex);
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intel_i2c_reset(dev);
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return 0;
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}
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