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Julia reported that the document looked unfinished, and it is. I forgot to include the example cooked up by Paul here: https://lkml.kernel.org/r/20170731174345.GL3730@linux.vnet.ibm.com and I added an explicit example showing how, while it is an ACQUIRE pattern, it really does provide an MB. Reported-by: Julia Cartwright <julia@ni.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Ingo Molnar <mingo@kernel.org>
243 lines
5.5 KiB
Plaintext
243 lines
5.5 KiB
Plaintext
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On atomic types (atomic_t atomic64_t and atomic_long_t).
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The atomic type provides an interface to the architecture's means of atomic
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RMW operations between CPUs (atomic operations on MMIO are not supported and
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can lead to fatal traps on some platforms).
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API
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---
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The 'full' API consists of (atomic64_ and atomic_long_ prefixes omitted for
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brevity):
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Non-RMW ops:
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atomic_read(), atomic_set()
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atomic_read_acquire(), atomic_set_release()
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RMW atomic operations:
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Arithmetic:
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atomic_{add,sub,inc,dec}()
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atomic_{add,sub,inc,dec}_return{,_relaxed,_acquire,_release}()
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atomic_fetch_{add,sub,inc,dec}{,_relaxed,_acquire,_release}()
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Bitwise:
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atomic_{and,or,xor,andnot}()
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atomic_fetch_{and,or,xor,andnot}{,_relaxed,_acquire,_release}()
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Swap:
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atomic_xchg{,_relaxed,_acquire,_release}()
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atomic_cmpxchg{,_relaxed,_acquire,_release}()
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atomic_try_cmpxchg{,_relaxed,_acquire,_release}()
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Reference count (but please see refcount_t):
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atomic_add_unless(), atomic_inc_not_zero()
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atomic_sub_and_test(), atomic_dec_and_test()
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Misc:
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atomic_inc_and_test(), atomic_add_negative()
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atomic_dec_unless_positive(), atomic_inc_unless_negative()
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Barriers:
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smp_mb__{before,after}_atomic()
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SEMANTICS
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---------
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Non-RMW ops:
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The non-RMW ops are (typically) regular LOADs and STOREs and are canonically
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implemented using READ_ONCE(), WRITE_ONCE(), smp_load_acquire() and
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smp_store_release() respectively.
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The one detail to this is that atomic_set{}() should be observable to the RMW
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ops. That is:
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C atomic-set
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{
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atomic_set(v, 1);
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}
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P1(atomic_t *v)
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{
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atomic_add_unless(v, 1, 0);
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}
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P2(atomic_t *v)
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{
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atomic_set(v, 0);
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}
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exists
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(v=2)
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In this case we would expect the atomic_set() from CPU1 to either happen
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before the atomic_add_unless(), in which case that latter one would no-op, or
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_after_ in which case we'd overwrite its result. In no case is "2" a valid
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outcome.
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This is typically true on 'normal' platforms, where a regular competing STORE
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will invalidate a LL/SC or fail a CMPXCHG.
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The obvious case where this is not so is when we need to implement atomic ops
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with a lock:
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CPU0 CPU1
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atomic_add_unless(v, 1, 0);
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lock();
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ret = READ_ONCE(v->counter); // == 1
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atomic_set(v, 0);
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if (ret != u) WRITE_ONCE(v->counter, 0);
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WRITE_ONCE(v->counter, ret + 1);
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unlock();
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the typical solution is to then implement atomic_set{}() with atomic_xchg().
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RMW ops:
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These come in various forms:
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- plain operations without return value: atomic_{}()
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- operations which return the modified value: atomic_{}_return()
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these are limited to the arithmetic operations because those are
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reversible. Bitops are irreversible and therefore the modified value
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is of dubious utility.
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- operations which return the original value: atomic_fetch_{}()
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- swap operations: xchg(), cmpxchg() and try_cmpxchg()
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- misc; the special purpose operations that are commonly used and would,
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given the interface, normally be implemented using (try_)cmpxchg loops but
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are time critical and can, (typically) on LL/SC architectures, be more
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efficiently implemented.
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All these operations are SMP atomic; that is, the operations (for a single
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atomic variable) can be fully ordered and no intermediate state is lost or
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visible.
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ORDERING (go read memory-barriers.txt first)
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--------
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The rule of thumb:
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- non-RMW operations are unordered;
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- RMW operations that have no return value are unordered;
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- RMW operations that have a return value are fully ordered;
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- RMW operations that are conditional are unordered on FAILURE,
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otherwise the above rules apply.
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Except of course when an operation has an explicit ordering like:
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{}_relaxed: unordered
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{}_acquire: the R of the RMW (or atomic_read) is an ACQUIRE
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{}_release: the W of the RMW (or atomic_set) is a RELEASE
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Where 'unordered' is against other memory locations. Address dependencies are
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not defeated.
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Fully ordered primitives are ordered against everything prior and everything
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subsequent. Therefore a fully ordered primitive is like having an smp_mb()
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before and an smp_mb() after the primitive.
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The barriers:
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smp_mb__{before,after}_atomic()
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only apply to the RMW ops and can be used to augment/upgrade the ordering
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inherent to the used atomic op. These barriers provide a full smp_mb().
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These helper barriers exist because architectures have varying implicit
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ordering on their SMP atomic primitives. For example our TSO architectures
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provide full ordered atomics and these barriers are no-ops.
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Thus:
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atomic_fetch_add();
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is equivalent to:
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smp_mb__before_atomic();
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atomic_fetch_add_relaxed();
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smp_mb__after_atomic();
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However the atomic_fetch_add() might be implemented more efficiently.
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Further, while something like:
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smp_mb__before_atomic();
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atomic_dec(&X);
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is a 'typical' RELEASE pattern, the barrier is strictly stronger than
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a RELEASE. Similarly for something like:
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atomic_inc(&X);
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smp_mb__after_atomic();
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is an ACQUIRE pattern (though very much not typical), but again the barrier is
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strictly stronger than ACQUIRE. As illustrated:
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C strong-acquire
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{
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}
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P1(int *x, atomic_t *y)
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{
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r0 = READ_ONCE(*x);
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smp_rmb();
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r1 = atomic_read(y);
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}
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P2(int *x, atomic_t *y)
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{
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atomic_inc(y);
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smp_mb__after_atomic();
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WRITE_ONCE(*x, 1);
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}
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exists
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(r0=1 /\ r1=0)
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This should not happen; but a hypothetical atomic_inc_acquire() --
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(void)atomic_fetch_inc_acquire() for instance -- would allow the outcome,
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since then:
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P1 P2
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t = LL.acq *y (0)
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t++;
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*x = 1;
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r0 = *x (1)
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RMB
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r1 = *y (0)
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SC *y, t;
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is allowed.
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