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800 lines
13 KiB
ArmAsm
800 lines
13 KiB
ArmAsm
/*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <mach/irq.h>
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#include <asm/dpmc.h>
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.section .l1.text
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ENTRY(_sleep_mode)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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call _set_rtc_istat;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R1 = W[P0](z);
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BITSET (R1, 3);
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W[P0] = R1.L;
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CLI R2;
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SSYNC;
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IDLE;
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STI R2;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R7 = w[p0](z);
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BITCLR (R7, 3);
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BITCLR (R7, 5);
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w[p0] = R7.L;
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IDLE;
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call _test_pll_locked;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENDPROC(_sleep_mode)
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ENTRY(_hibernate_mode)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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R3 = R0;
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R0 = IWR_DISABLE_ALL;
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs;
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SSYNC;
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R0 = 0xFFFF (Z);
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call _set_rtc_istat;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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W[P0] = R3.L;
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CLI R2;
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IDLE;
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.Lforever:
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jump .Lforever;
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ENDPROC(_hibernate_mode)
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ENTRY(_sleep_deeper)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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CLI R4;
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P3 = R0;
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P4 = R1;
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P5 = R2;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs; /* Set SDRAM Self Refresh */
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/* Clear all the interrupts,bits sticky */
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R0 = 0xFFFF (Z);
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call _set_rtc_istat;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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R6 = W[P0](z);
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R0.L = 0xF;
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W[P0] = R0.l; /* Set Max VCO to SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R5 = W[P0](z);
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R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
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W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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R7 = W[P0](z);
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R1 = 0x6;
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R1 <<= 16;
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R2 = 0x0404(Z);
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R1 = R1|R2;
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R2 = DEPOSIT(R7, R1);
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W[P0] = R2; /* Set Min Core Voltage */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = P3;
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R1 = P4;
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R3 = P5;
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call _set_sic_iwr; /* Set Awake from IDLE */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 3);
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W[P0] = R0.L; /* Turn CCLK OFF */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr; /* Set Awake from IDLE PLL */
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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W[P0]= R7;
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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W[P0]= R6; /* Restore CCLK and SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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w[p0] = R5; /* Restore VCO multiplier */
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IDLE;
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call _test_pll_locked;
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call _unset_dram_srfs; /* SDRAM Self Refresh Off */
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STI R4;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENDPROC(_sleep_deeper)
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ENTRY(_set_dram_srfs)
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/* set the dram to self refresh mode */
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SSYNC;
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#if defined(EBIU_RSTCTL) /* DDR */
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P0.H = hi(EBIU_RSTCTL);
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P0.L = lo(EBIU_RSTCTL);
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R2 = [P0];
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BITSET(R2, 3); /* SRREQ enter self-refresh mode */
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[P0] = R2;
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SSYNC;
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1:
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R2 = [P0];
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CC = BITTST(R2, 4);
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if !CC JUMP 1b;
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#else /* SDRAM */
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P0.L = lo(EBIU_SDGCTL);
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P0.H = hi(EBIU_SDGCTL);
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R2 = [P0];
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BITSET(R2, 24); /* SRFS enter self-refresh mode */
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[P0] = R2;
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SSYNC;
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P0.L = lo(EBIU_SDSTAT);
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P0.H = hi(EBIU_SDSTAT);
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1:
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R2 = w[P0];
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SSYNC;
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cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
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if !cc jump 1b;
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P0.L = lo(EBIU_SDGCTL);
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P0.H = hi(EBIU_SDGCTL);
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R2 = [P0];
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BITCLR(R2, 0); /* SCTLE disable CLKOUT */
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[P0] = R2;
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#endif
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RTS;
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ENDPROC(_set_dram_srfs)
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ENTRY(_unset_dram_srfs)
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/* set the dram out of self refresh mode */
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#if defined(EBIU_RSTCTL) /* DDR */
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P0.H = hi(EBIU_RSTCTL);
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P0.L = lo(EBIU_RSTCTL);
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R2 = [P0];
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BITCLR(R2, 3); /* clear SRREQ bit */
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[P0] = R2;
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#elif defined(EBIU_SDGCTL) /* SDRAM */
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P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
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P0.H = hi(EBIU_SDGCTL);
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R2 = [P0];
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BITSET(R2, 0); /* SCTLE enable CLKOUT */
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[P0] = R2
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SSYNC;
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P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
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P0.H = hi(EBIU_SDGCTL);
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R2 = [P0];
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BITCLR(R2, 24); /* clear SRFS bit */
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[P0] = R2
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#endif
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SSYNC;
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RTS;
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ENDPROC(_unset_dram_srfs)
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ENTRY(_set_sic_iwr)
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
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P0.H = hi(SIC_IWR0);
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P0.L = lo(SIC_IWR0);
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P1.H = hi(SIC_IWR1);
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P1.L = lo(SIC_IWR1);
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[P1] = R1;
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#if defined(CONFIG_BF54x)
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P1.H = hi(SIC_IWR2);
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P1.L = lo(SIC_IWR2);
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[P1] = R2;
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#endif
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#else
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P0.H = hi(SIC_IWR);
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P0.L = lo(SIC_IWR);
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#endif
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[P0] = R0;
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SSYNC;
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RTS;
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ENDPROC(_set_sic_iwr)
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ENTRY(_set_rtc_istat)
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#ifndef CONFIG_BF561
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P0.H = hi(RTC_ISTAT);
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P0.L = lo(RTC_ISTAT);
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w[P0] = R0.L;
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SSYNC;
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#elif (ANOMALY_05000371)
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nop;
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nop;
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nop;
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nop;
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#endif
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RTS;
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ENDPROC(_set_rtc_istat)
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ENTRY(_test_pll_locked)
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P0.H = hi(PLL_STAT);
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P0.L = lo(PLL_STAT);
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1:
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R0 = W[P0] (Z);
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CC = BITTST(R0,5);
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IF !CC JUMP 1b;
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RTS;
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ENDPROC(_test_pll_locked)
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.section .text
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ENTRY(_do_hibernate)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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/* Save System MMRs */
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R2 = R0;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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#ifdef SIC_IMASK0
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PM_SYS_PUSH(SIC_IMASK0)
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#endif
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#ifdef SIC_IMASK1
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PM_SYS_PUSH(SIC_IMASK1)
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#endif
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#ifdef SIC_IMASK2
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PM_SYS_PUSH(SIC_IMASK2)
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#endif
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#ifdef SIC_IMASK
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PM_SYS_PUSH(SIC_IMASK)
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#endif
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#ifdef SICA_IMASK0
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PM_SYS_PUSH(SICA_IMASK0)
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#endif
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#ifdef SICA_IMASK1
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PM_SYS_PUSH(SICA_IMASK1)
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#endif
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#ifdef SIC_IAR2
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PM_SYS_PUSH(SIC_IAR0)
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PM_SYS_PUSH(SIC_IAR1)
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PM_SYS_PUSH(SIC_IAR2)
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#endif
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#ifdef SIC_IAR3
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PM_SYS_PUSH(SIC_IAR3)
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#endif
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#ifdef SIC_IAR4
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PM_SYS_PUSH(SIC_IAR4)
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PM_SYS_PUSH(SIC_IAR5)
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PM_SYS_PUSH(SIC_IAR6)
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#endif
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#ifdef SIC_IAR7
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PM_SYS_PUSH(SIC_IAR7)
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#endif
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#ifdef SIC_IAR8
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PM_SYS_PUSH(SIC_IAR8)
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PM_SYS_PUSH(SIC_IAR9)
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PM_SYS_PUSH(SIC_IAR10)
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PM_SYS_PUSH(SIC_IAR11)
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#endif
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#ifdef SICA_IAR0
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PM_SYS_PUSH(SICA_IAR0)
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PM_SYS_PUSH(SICA_IAR1)
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PM_SYS_PUSH(SICA_IAR2)
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PM_SYS_PUSH(SICA_IAR3)
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PM_SYS_PUSH(SICA_IAR4)
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PM_SYS_PUSH(SICA_IAR5)
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PM_SYS_PUSH(SICA_IAR6)
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PM_SYS_PUSH(SICA_IAR7)
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#endif
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#ifdef SIC_IWR
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PM_SYS_PUSH(SIC_IWR)
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#endif
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#ifdef SIC_IWR0
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PM_SYS_PUSH(SIC_IWR0)
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#endif
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#ifdef SIC_IWR1
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PM_SYS_PUSH(SIC_IWR1)
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#endif
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#ifdef SIC_IWR2
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PM_SYS_PUSH(SIC_IWR2)
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#endif
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#ifdef SICA_IWR0
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PM_SYS_PUSH(SICA_IWR0)
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#endif
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#ifdef SICA_IWR1
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PM_SYS_PUSH(SICA_IWR1)
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#endif
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#ifdef PINT0_ASSIGN
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PM_SYS_PUSH(PINT0_ASSIGN)
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PM_SYS_PUSH(PINT1_ASSIGN)
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PM_SYS_PUSH(PINT2_ASSIGN)
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PM_SYS_PUSH(PINT3_ASSIGN)
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#endif
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PM_SYS_PUSH(EBIU_AMBCTL0)
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PM_SYS_PUSH(EBIU_AMBCTL1)
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PM_SYS_PUSH16(EBIU_AMGCTL)
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#ifdef EBIU_FCTL
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PM_SYS_PUSH(EBIU_MBSCTL)
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PM_SYS_PUSH(EBIU_MODE)
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PM_SYS_PUSH(EBIU_FCTL)
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#endif
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PM_SYS_PUSH16(SYSCR)
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/* Save Core MMRs */
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P0.H = hi(SRAM_BASE_ADDRESS);
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P0.L = lo(SRAM_BASE_ADDRESS);
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PM_PUSH(DMEM_CONTROL)
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PM_PUSH(DCPLB_ADDR0)
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PM_PUSH(DCPLB_ADDR1)
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PM_PUSH(DCPLB_ADDR2)
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PM_PUSH(DCPLB_ADDR3)
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PM_PUSH(DCPLB_ADDR4)
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PM_PUSH(DCPLB_ADDR5)
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PM_PUSH(DCPLB_ADDR6)
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PM_PUSH(DCPLB_ADDR7)
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PM_PUSH(DCPLB_ADDR8)
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PM_PUSH(DCPLB_ADDR9)
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PM_PUSH(DCPLB_ADDR10)
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PM_PUSH(DCPLB_ADDR11)
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PM_PUSH(DCPLB_ADDR12)
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PM_PUSH(DCPLB_ADDR13)
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PM_PUSH(DCPLB_ADDR14)
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PM_PUSH(DCPLB_ADDR15)
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PM_PUSH(DCPLB_DATA0)
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PM_PUSH(DCPLB_DATA1)
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PM_PUSH(DCPLB_DATA2)
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PM_PUSH(DCPLB_DATA3)
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PM_PUSH(DCPLB_DATA4)
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PM_PUSH(DCPLB_DATA5)
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PM_PUSH(DCPLB_DATA6)
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PM_PUSH(DCPLB_DATA7)
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PM_PUSH(DCPLB_DATA8)
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PM_PUSH(DCPLB_DATA9)
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PM_PUSH(DCPLB_DATA10)
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PM_PUSH(DCPLB_DATA11)
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PM_PUSH(DCPLB_DATA12)
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PM_PUSH(DCPLB_DATA13)
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PM_PUSH(DCPLB_DATA14)
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PM_PUSH(DCPLB_DATA15)
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PM_PUSH(IMEM_CONTROL)
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PM_PUSH(ICPLB_ADDR0)
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PM_PUSH(ICPLB_ADDR1)
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PM_PUSH(ICPLB_ADDR2)
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PM_PUSH(ICPLB_ADDR3)
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PM_PUSH(ICPLB_ADDR4)
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PM_PUSH(ICPLB_ADDR5)
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PM_PUSH(ICPLB_ADDR6)
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PM_PUSH(ICPLB_ADDR7)
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PM_PUSH(ICPLB_ADDR8)
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PM_PUSH(ICPLB_ADDR9)
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PM_PUSH(ICPLB_ADDR10)
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PM_PUSH(ICPLB_ADDR11)
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PM_PUSH(ICPLB_ADDR12)
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PM_PUSH(ICPLB_ADDR13)
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PM_PUSH(ICPLB_ADDR14)
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PM_PUSH(ICPLB_ADDR15)
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PM_PUSH(ICPLB_DATA0)
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PM_PUSH(ICPLB_DATA1)
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PM_PUSH(ICPLB_DATA2)
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PM_PUSH(ICPLB_DATA3)
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PM_PUSH(ICPLB_DATA4)
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PM_PUSH(ICPLB_DATA5)
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PM_PUSH(ICPLB_DATA6)
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PM_PUSH(ICPLB_DATA7)
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PM_PUSH(ICPLB_DATA8)
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PM_PUSH(ICPLB_DATA9)
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PM_PUSH(ICPLB_DATA10)
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PM_PUSH(ICPLB_DATA11)
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PM_PUSH(ICPLB_DATA12)
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PM_PUSH(ICPLB_DATA13)
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PM_PUSH(ICPLB_DATA14)
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PM_PUSH(ICPLB_DATA15)
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PM_PUSH(EVT0)
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PM_PUSH(EVT1)
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PM_PUSH(EVT2)
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PM_PUSH(EVT3)
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PM_PUSH(EVT4)
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PM_PUSH(EVT5)
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PM_PUSH(EVT6)
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PM_PUSH(EVT7)
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PM_PUSH(EVT8)
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PM_PUSH(EVT9)
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PM_PUSH(EVT10)
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PM_PUSH(EVT11)
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PM_PUSH(EVT12)
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PM_PUSH(EVT13)
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PM_PUSH(EVT14)
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PM_PUSH(EVT15)
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PM_PUSH(IMASK)
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PM_PUSH(ILAT)
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PM_PUSH(IPRIO)
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PM_PUSH(TCNTL)
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PM_PUSH(TPERIOD)
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PM_PUSH(TSCALE)
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PM_PUSH(TCOUNT)
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PM_PUSH(TBUFCTL)
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/* Save Core Registers */
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[--sp] = SYSCFG;
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[--sp] = ( R7:0, P5:0 );
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[--sp] = fp;
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[--sp] = usp;
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[--sp] = i0;
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[--sp] = i1;
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[--sp] = i2;
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[--sp] = i3;
|
|
|
|
[--sp] = m0;
|
|
[--sp] = m1;
|
|
[--sp] = m2;
|
|
[--sp] = m3;
|
|
|
|
[--sp] = l0;
|
|
[--sp] = l1;
|
|
[--sp] = l2;
|
|
[--sp] = l3;
|
|
|
|
[--sp] = b0;
|
|
[--sp] = b1;
|
|
[--sp] = b2;
|
|
[--sp] = b3;
|
|
[--sp] = a0.x;
|
|
[--sp] = a0.w;
|
|
[--sp] = a1.x;
|
|
[--sp] = a1.w;
|
|
|
|
[--sp] = LC0;
|
|
[--sp] = LC1;
|
|
[--sp] = LT0;
|
|
[--sp] = LT1;
|
|
[--sp] = LB0;
|
|
[--sp] = LB1;
|
|
|
|
[--sp] = ASTAT;
|
|
[--sp] = CYCLES;
|
|
[--sp] = CYCLES2;
|
|
|
|
[--sp] = RETS;
|
|
r0 = RETI;
|
|
[--sp] = r0;
|
|
[--sp] = RETX;
|
|
[--sp] = RETN;
|
|
[--sp] = RETE;
|
|
[--sp] = SEQSTAT;
|
|
|
|
/* Save Magic, return address and Stack Pointer */
|
|
P0.H = 0;
|
|
P0.L = 0;
|
|
R0.H = 0xDEAD; /* Hibernate Magic */
|
|
R0.L = 0xBEEF;
|
|
[P0++] = R0; /* Store Hibernate Magic */
|
|
R0.H = .Lpm_resume_here;
|
|
R0.L = .Lpm_resume_here;
|
|
[P0++] = R0; /* Save Return Address */
|
|
[P0++] = SP; /* Save Stack Pointer */
|
|
P0.H = _hibernate_mode;
|
|
P0.L = _hibernate_mode;
|
|
R0 = R2;
|
|
call (P0); /* Goodbye */
|
|
|
|
.Lpm_resume_here:
|
|
|
|
/* Restore Core Registers */
|
|
SEQSTAT = [sp++];
|
|
RETE = [sp++];
|
|
RETN = [sp++];
|
|
RETX = [sp++];
|
|
r0 = [sp++];
|
|
RETI = r0;
|
|
RETS = [sp++];
|
|
|
|
CYCLES2 = [sp++];
|
|
CYCLES = [sp++];
|
|
ASTAT = [sp++];
|
|
|
|
LB1 = [sp++];
|
|
LB0 = [sp++];
|
|
LT1 = [sp++];
|
|
LT0 = [sp++];
|
|
LC1 = [sp++];
|
|
LC0 = [sp++];
|
|
|
|
a1.w = [sp++];
|
|
a1.x = [sp++];
|
|
a0.w = [sp++];
|
|
a0.x = [sp++];
|
|
b3 = [sp++];
|
|
b2 = [sp++];
|
|
b1 = [sp++];
|
|
b0 = [sp++];
|
|
|
|
l3 = [sp++];
|
|
l2 = [sp++];
|
|
l1 = [sp++];
|
|
l0 = [sp++];
|
|
|
|
m3 = [sp++];
|
|
m2 = [sp++];
|
|
m1 = [sp++];
|
|
m0 = [sp++];
|
|
|
|
i3 = [sp++];
|
|
i2 = [sp++];
|
|
i1 = [sp++];
|
|
i0 = [sp++];
|
|
|
|
usp = [sp++];
|
|
fp = [sp++];
|
|
|
|
( R7 : 0, P5 : 0) = [ SP ++ ];
|
|
SYSCFG = [sp++];
|
|
|
|
/* Restore Core MMRs */
|
|
|
|
PM_POP(TBUFCTL)
|
|
PM_POP(TCOUNT)
|
|
PM_POP(TSCALE)
|
|
PM_POP(TPERIOD)
|
|
PM_POP(TCNTL)
|
|
PM_POP(IPRIO)
|
|
PM_POP(ILAT)
|
|
PM_POP(IMASK)
|
|
PM_POP(EVT15)
|
|
PM_POP(EVT14)
|
|
PM_POP(EVT13)
|
|
PM_POP(EVT12)
|
|
PM_POP(EVT11)
|
|
PM_POP(EVT10)
|
|
PM_POP(EVT9)
|
|
PM_POP(EVT8)
|
|
PM_POP(EVT7)
|
|
PM_POP(EVT6)
|
|
PM_POP(EVT5)
|
|
PM_POP(EVT4)
|
|
PM_POP(EVT3)
|
|
PM_POP(EVT2)
|
|
PM_POP(EVT1)
|
|
PM_POP(EVT0)
|
|
PM_POP(ICPLB_DATA15)
|
|
PM_POP(ICPLB_DATA14)
|
|
PM_POP(ICPLB_DATA13)
|
|
PM_POP(ICPLB_DATA12)
|
|
PM_POP(ICPLB_DATA11)
|
|
PM_POP(ICPLB_DATA10)
|
|
PM_POP(ICPLB_DATA9)
|
|
PM_POP(ICPLB_DATA8)
|
|
PM_POP(ICPLB_DATA7)
|
|
PM_POP(ICPLB_DATA6)
|
|
PM_POP(ICPLB_DATA5)
|
|
PM_POP(ICPLB_DATA4)
|
|
PM_POP(ICPLB_DATA3)
|
|
PM_POP(ICPLB_DATA2)
|
|
PM_POP(ICPLB_DATA1)
|
|
PM_POP(ICPLB_DATA0)
|
|
PM_POP(ICPLB_ADDR15)
|
|
PM_POP(ICPLB_ADDR14)
|
|
PM_POP(ICPLB_ADDR13)
|
|
PM_POP(ICPLB_ADDR12)
|
|
PM_POP(ICPLB_ADDR11)
|
|
PM_POP(ICPLB_ADDR10)
|
|
PM_POP(ICPLB_ADDR9)
|
|
PM_POP(ICPLB_ADDR8)
|
|
PM_POP(ICPLB_ADDR7)
|
|
PM_POP(ICPLB_ADDR6)
|
|
PM_POP(ICPLB_ADDR5)
|
|
PM_POP(ICPLB_ADDR4)
|
|
PM_POP(ICPLB_ADDR3)
|
|
PM_POP(ICPLB_ADDR2)
|
|
PM_POP(ICPLB_ADDR1)
|
|
PM_POP(ICPLB_ADDR0)
|
|
PM_POP(IMEM_CONTROL)
|
|
PM_POP(DCPLB_DATA15)
|
|
PM_POP(DCPLB_DATA14)
|
|
PM_POP(DCPLB_DATA13)
|
|
PM_POP(DCPLB_DATA12)
|
|
PM_POP(DCPLB_DATA11)
|
|
PM_POP(DCPLB_DATA10)
|
|
PM_POP(DCPLB_DATA9)
|
|
PM_POP(DCPLB_DATA8)
|
|
PM_POP(DCPLB_DATA7)
|
|
PM_POP(DCPLB_DATA6)
|
|
PM_POP(DCPLB_DATA5)
|
|
PM_POP(DCPLB_DATA4)
|
|
PM_POP(DCPLB_DATA3)
|
|
PM_POP(DCPLB_DATA2)
|
|
PM_POP(DCPLB_DATA1)
|
|
PM_POP(DCPLB_DATA0)
|
|
PM_POP(DCPLB_ADDR15)
|
|
PM_POP(DCPLB_ADDR14)
|
|
PM_POP(DCPLB_ADDR13)
|
|
PM_POP(DCPLB_ADDR12)
|
|
PM_POP(DCPLB_ADDR11)
|
|
PM_POP(DCPLB_ADDR10)
|
|
PM_POP(DCPLB_ADDR9)
|
|
PM_POP(DCPLB_ADDR8)
|
|
PM_POP(DCPLB_ADDR7)
|
|
PM_POP(DCPLB_ADDR6)
|
|
PM_POP(DCPLB_ADDR5)
|
|
PM_POP(DCPLB_ADDR4)
|
|
PM_POP(DCPLB_ADDR3)
|
|
PM_POP(DCPLB_ADDR2)
|
|
PM_POP(DCPLB_ADDR1)
|
|
PM_POP(DCPLB_ADDR0)
|
|
PM_POP(DMEM_CONTROL)
|
|
|
|
/* Restore System MMRs */
|
|
|
|
P0.H = hi(PLL_CTL);
|
|
P0.L = lo(PLL_CTL);
|
|
PM_SYS_POP16(SYSCR)
|
|
|
|
#ifdef EBIU_FCTL
|
|
PM_SYS_POP(EBIU_FCTL)
|
|
PM_SYS_POP(EBIU_MODE)
|
|
PM_SYS_POP(EBIU_MBSCTL)
|
|
#endif
|
|
PM_SYS_POP16(EBIU_AMGCTL)
|
|
PM_SYS_POP(EBIU_AMBCTL1)
|
|
PM_SYS_POP(EBIU_AMBCTL0)
|
|
|
|
#ifdef PINT0_ASSIGN
|
|
PM_SYS_POP(PINT3_ASSIGN)
|
|
PM_SYS_POP(PINT2_ASSIGN)
|
|
PM_SYS_POP(PINT1_ASSIGN)
|
|
PM_SYS_POP(PINT0_ASSIGN)
|
|
#endif
|
|
|
|
#ifdef SICA_IWR1
|
|
PM_SYS_POP(SICA_IWR1)
|
|
#endif
|
|
#ifdef SICA_IWR0
|
|
PM_SYS_POP(SICA_IWR0)
|
|
#endif
|
|
#ifdef SIC_IWR2
|
|
PM_SYS_POP(SIC_IWR2)
|
|
#endif
|
|
#ifdef SIC_IWR1
|
|
PM_SYS_POP(SIC_IWR1)
|
|
#endif
|
|
#ifdef SIC_IWR0
|
|
PM_SYS_POP(SIC_IWR0)
|
|
#endif
|
|
#ifdef SIC_IWR
|
|
PM_SYS_POP(SIC_IWR)
|
|
#endif
|
|
|
|
#ifdef SICA_IAR0
|
|
PM_SYS_POP(SICA_IAR7)
|
|
PM_SYS_POP(SICA_IAR6)
|
|
PM_SYS_POP(SICA_IAR5)
|
|
PM_SYS_POP(SICA_IAR4)
|
|
PM_SYS_POP(SICA_IAR3)
|
|
PM_SYS_POP(SICA_IAR2)
|
|
PM_SYS_POP(SICA_IAR1)
|
|
PM_SYS_POP(SICA_IAR0)
|
|
#endif
|
|
|
|
#ifdef SIC_IAR8
|
|
PM_SYS_POP(SIC_IAR11)
|
|
PM_SYS_POP(SIC_IAR10)
|
|
PM_SYS_POP(SIC_IAR9)
|
|
PM_SYS_POP(SIC_IAR8)
|
|
#endif
|
|
#ifdef SIC_IAR7
|
|
PM_SYS_POP(SIC_IAR7)
|
|
#endif
|
|
#ifdef SIC_IAR6
|
|
PM_SYS_POP(SIC_IAR6)
|
|
PM_SYS_POP(SIC_IAR5)
|
|
PM_SYS_POP(SIC_IAR4)
|
|
#endif
|
|
#ifdef SIC_IAR3
|
|
PM_SYS_POP(SIC_IAR3)
|
|
#endif
|
|
#ifdef SIC_IAR2
|
|
PM_SYS_POP(SIC_IAR2)
|
|
PM_SYS_POP(SIC_IAR1)
|
|
PM_SYS_POP(SIC_IAR0)
|
|
#endif
|
|
#ifdef SICA_IMASK1
|
|
PM_SYS_POP(SICA_IMASK1)
|
|
#endif
|
|
#ifdef SICA_IMASK0
|
|
PM_SYS_POP(SICA_IMASK0)
|
|
#endif
|
|
#ifdef SIC_IMASK
|
|
PM_SYS_POP(SIC_IMASK)
|
|
#endif
|
|
#ifdef SIC_IMASK2
|
|
PM_SYS_POP(SIC_IMASK2)
|
|
#endif
|
|
#ifdef SIC_IMASK1
|
|
PM_SYS_POP(SIC_IMASK1)
|
|
#endif
|
|
#ifdef SIC_IMASK0
|
|
PM_SYS_POP(SIC_IMASK0)
|
|
#endif
|
|
|
|
[--sp] = RETI; /* Clear Global Interrupt Disable */
|
|
SP += 4;
|
|
|
|
RETS = [SP++];
|
|
( R7:0, P5:0 ) = [SP++];
|
|
RTS;
|
|
ENDPROC(_do_hibernate)
|